/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef _GVT_REG_H #define _GVT_REG_H #define INTEL_GVT_PCI_CLASS_VGA_OTHER … #define INTEL_GVT_PCI_GMCH_CONTROL … #define BDW_GMCH_GMS_SHIFT … #define BDW_GMCH_GMS_MASK … #define INTEL_GVT_PCI_SWSCI … #define SWSCI_SCI_SELECT … #define SWSCI_SCI_TRIGGER … #define INTEL_GVT_PCI_OPREGION … #define INTEL_GVT_OPREGION_CLID … #define INTEL_GVT_OPREGION_SCIC … #define OPREGION_SCIC_FUNC_MASK … #define OPREGION_SCIC_FUNC_SHIFT … #define OPREGION_SCIC_SUBFUNC_MASK … #define OPREGION_SCIC_SUBFUNC_SHIFT … #define OPREGION_SCIC_EXIT_MASK … #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA … #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS … #define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS … #define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS … #define INTEL_GVT_OPREGION_PARM … #define INTEL_GVT_OPREGION_PAGES … #define INTEL_GVT_OPREGION_SIZE … #define INTEL_GVT_OPREGION_VBT_OFFSET … #define INTEL_GVT_OPREGION_VBT_SIZE … #define VGT_SPRSTRIDE(pipe) … #define SKL_FLIP_EVENT(pipe, plane) … #define REG50080_FLIP_TYPE_MASK … #define REG50080_FLIP_TYPE_ASYNC … #define REG_50080(_pipe, _plane) … #define REG_50080_TO_PIPE(_reg) … #define REG_50080_TO_PLANE(_reg) … #define GFX_MODE_BIT_SET_IN_MASK(val, bit) … #define IS_MASKED_BITS_ENABLED(_val, _b) … #define IS_MASKED_BITS_DISABLED(_val, _b) … #define FORCEWAKE_RENDER_GEN9_REG … #define FORCEWAKE_ACK_RENDER_GEN9_REG … #define FORCEWAKE_GT_GEN9_REG … #define FORCEWAKE_ACK_GT_GEN9_REG … #define FORCEWAKE_MEDIA_GEN9_REG … #define FORCEWAKE_ACK_MEDIA_GEN9_REG … #define FORCEWAKE_ACK_HSW_REG … #define RB_HEAD_WRAP_CNT_MAX … #define RB_HEAD_WRAP_CNT_OFF … #define RB_HEAD_OFF_MASK … #define RB_TAIL_OFF_MASK … #define RB_TAIL_SIZE_MASK … #define _RING_CTL_BUF_SIZE(ctl) … #define PCH_GPIO_BASE … #define PCH_GMBUS0 … #define PCH_GMBUS1 … #define PCH_GMBUS2 … #define PCH_GMBUS3 … #define PCH_GMBUS4 … #define PCH_GMBUS5 … #define TRVATTL3PTRDW(i) … #define TRNULLDETCT … #define TRINVTILEDETCT … #define TRVADR … #define TRTTE … #define RING_EXCC(base) … #define RING_GFX_MODE(base) … #define VF_GUARDBAND … #define BCS_TILE_REGISTER_VAL_OFFSET … /* XXX FIXME i915 has changed PP_XXX definition */ #define PCH_PP_STATUS … #define PCH_PP_CONTROL … #define PCH_PP_ON_DELAYS … #define PCH_PP_OFF_DELAYS … #define PCH_PP_DIVISOR … #endif
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