linux/drivers/gpu/drm/i915/gvt/interrupt.h

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Kevin Tian <[email protected]>
 *    Zhi Wang <[email protected]>
 *
 * Contributors:
 *    Min he <[email protected]>
 *
 */

#ifndef _GVT_INTERRUPT_H_
#define _GVT_INTERRUPT_H_

#include <linux/bitops.h>

struct intel_gvt;
struct intel_gvt_irq;
struct intel_gvt_irq_info;
struct intel_gvt_irq_map;
struct intel_vgpu;

enum intel_gvt_event_type { … };

gvt_event_virt_handler_t;

struct intel_gvt_irq_ops { … };

/* the list of physical interrupt control register groups */
enum intel_gvt_irq_type { … };

#define INTEL_GVT_IRQ_BITWIDTH …

/* per-event information */
struct intel_gvt_event_info { … };

/* structure containing device specific IRQ state */
struct intel_gvt_irq { … };

int intel_gvt_init_irq(struct intel_gvt *gvt);

void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
	enum intel_gvt_event_type event);

int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
	void *p_data, unsigned int bytes);
int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
	unsigned int reg, void *p_data, unsigned int bytes);
int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
	unsigned int reg, void *p_data, unsigned int bytes);
int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
	unsigned int reg, void *p_data, unsigned int bytes);

int gvt_ring_id_to_pipe_control_notify_event(int ring_id);
int gvt_ring_id_to_mi_flush_dw_event(int ring_id);
int gvt_ring_id_to_mi_user_interrupt_event(int ring_id);

#endif /* _GVT_INTERRUPT_H_ */