/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Ke Yu * Zhiyuan Lv <[email protected]> * * Contributors: * Terrence Xu <[email protected]> * Changbin Du <[email protected]> * Bing Niu <[email protected]> * Zhi Wang <[email protected]> * */ #ifndef _GVT_DISPLAY_H_ #define _GVT_DISPLAY_H_ #include <linux/types.h> #include <linux/hrtimer.h> struct intel_gvt; struct intel_vgpu; #define SBI_REG_MAX … #define DPCD_SIZE … #define intel_vgpu_port(vgpu, port) … #define intel_vgpu_has_monitor_on_port(vgpu, port) … #define intel_vgpu_port_is_dp(vgpu, port) … #define INTEL_GVT_MAX_UEVENT_VARS … /* DPCD start */ #define DPCD_SIZE … /* DPCD */ #define DP_SET_POWER … #define DP_SET_POWER_D0 … #define AUX_NATIVE_WRITE … #define AUX_NATIVE_READ … #define AUX_NATIVE_REPLY_MASK … #define AUX_NATIVE_REPLY_ACK … #define AUX_NATIVE_REPLY_NAK … #define AUX_NATIVE_REPLY_DEFER … #define AUX_BURST_SIZE … /* DPCD addresses */ #define DPCD_REV … #define DPCD_MAX_LINK_RATE … #define DPCD_MAX_LANE_COUNT … #define DPCD_TRAINING_PATTERN_SET … #define DPCD_SINK_COUNT … #define DPCD_LANE0_1_STATUS … #define DPCD_LANE2_3_STATUS … #define DPCD_LANE_ALIGN_STATUS_UPDATED … #define DPCD_SINK_STATUS … /* link training */ #define DPCD_TRAINING_PATTERN_SET_MASK … #define DPCD_LINK_TRAINING_DISABLED … #define DPCD_TRAINING_PATTERN_1 … #define DPCD_TRAINING_PATTERN_2 … #define DPCD_CP_READY_MASK … /* lane status */ #define DPCD_LANES_CR_DONE … #define DPCD_LANES_EQ_DONE … #define DPCD_SYMBOL_LOCKED … #define DPCD_INTERLANE_ALIGN_DONE … #define DPCD_SINK_IN_SYNC … /* DPCD end */ #define SBI_RESPONSE_MASK … #define SBI_RESPONSE_SHIFT … #define SBI_STAT_MASK … #define SBI_STAT_SHIFT … #define SBI_OPCODE_SHIFT … #define SBI_OPCODE_MASK … #define SBI_CMD_IORD … #define SBI_CMD_IOWR … #define SBI_CMD_CRRD … #define SBI_CMD_CRWR … #define SBI_ADDR_OFFSET_SHIFT … #define SBI_ADDR_OFFSET_MASK … struct intel_vgpu_sbi_register { … }; struct intel_vgpu_sbi { … }; enum intel_gvt_plane_type { … }; struct intel_vgpu_dpcd_data { … }; enum intel_vgpu_port_type { … }; enum intel_vgpu_edid { … }; #define GVT_DEFAULT_REFRESH_RATE … struct intel_vgpu_port { … }; struct intel_vgpu_vblank_timer { … }; static inline char *vgpu_edid_str(enum intel_vgpu_edid id) { … } static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id) { … } static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id) { … } void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu); void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon); int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution); void intel_vgpu_reset_display(struct intel_vgpu *vgpu); void intel_vgpu_clean_display(struct intel_vgpu *vgpu); int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe); #endif
Codebase Browser
linux