/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Ke Yu * Zhiyuan Lv <[email protected]> * * Contributors: * Terrence Xu <[email protected]> * Changbin Du <[email protected]> * Bing Niu <[email protected]> * Zhi Wang <[email protected]> * */ #ifndef _GVT_EDID_H_ #define _GVT_EDID_H_ #include <linux/types.h> struct intel_vgpu; #define EDID_SIZE … #define EDID_ADDR … #define GVT_AUX_NATIVE_WRITE … #define GVT_AUX_NATIVE_READ … #define GVT_AUX_I2C_WRITE … #define GVT_AUX_I2C_READ … #define GVT_AUX_I2C_STATUS … #define GVT_AUX_I2C_MOT … #define GVT_AUX_I2C_REPLY_ACK … struct intel_vgpu_edid_data { … }; enum gmbus_cycle_type { … }; /* * States of GMBUS * * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are * not considered here. Below describes the usage of GMBUS registers that are * cared by the EDID virtualization * * GMBUS0: * R/W * port selection. value of bit0 - bit2 corresponds to the GPIO registers. * * GMBUS1: * R/W Protect * Command and Status. * bit0 is the direction bit: 1 is read; 0 is write. * bit1 - bit7 is target 7-bit address. * bit16 - bit24 total byte count (ignore?) * * GMBUS2: * Most of bits are read only except bit 15 (IN_USE) * Status register * bit0 - bit8 current byte count * bit 11: hardware ready; * * GMBUS3: * Read/Write * Data for transfer */ /* From hw specs, Other phases like START, ADDRESS, INDEX * are invisible to GMBUS MMIO interface. So no definitions * in below enum types */ enum gvt_gmbus_phase { … }; struct intel_vgpu_i2c_gmbus { … }; struct intel_vgpu_i2c_aux_ch { … }; enum i2c_state { … }; /* I2C sequences cannot interleave. * GMBUS and AUX_CH sequences cannot interleave. */ struct intel_vgpu_i2c_edid { … }; void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu); int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, int port_idx, unsigned int offset, void *p_data); #endif /*_GVT_EDID_H_*/
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