/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Kevin Tian <[email protected]> * * Contributors: * Bing Niu <[email protected]> * Xu Han <[email protected]> * Ping Gao <[email protected]> * Xiaoguang Chen <[email protected]> * Yang Liu <[email protected]> * Tina Zhang <[email protected]> * */ #ifndef _GVT_FB_DECODER_H_ #define _GVT_FB_DECODER_H_ #include <linux/types.h> #include "display/intel_display_limits.h" struct intel_vgpu; #define _PLANE_CTL_FORMAT_SHIFT … #define _PLANE_CTL_TILED_SHIFT … #define _PIPE_V_SRCSZ_SHIFT … #define _PIPE_V_SRCSZ_MASK … #define _PIPE_H_SRCSZ_SHIFT … #define _PIPE_H_SRCSZ_MASK … #define _PRI_PLANE_FMT_SHIFT … #define _PRI_PLANE_STRIDE_MASK … #define _PRI_PLANE_X_OFF_SHIFT … #define _PRI_PLANE_X_OFF_MASK … #define _PRI_PLANE_Y_OFF_SHIFT … #define _PRI_PLANE_Y_OFF_MASK … #define _CURSOR_MODE … #define _CURSOR_ALPHA_FORCE_SHIFT … #define _CURSOR_ALPHA_FORCE_MASK … #define _CURSOR_ALPHA_PLANE_SHIFT … #define _CURSOR_ALPHA_PLANE_MASK … #define _CURSOR_POS_X_SHIFT … #define _CURSOR_POS_X_MASK … #define _CURSOR_SIGN_X_SHIFT … #define _CURSOR_SIGN_X_MASK … #define _CURSOR_POS_Y_SHIFT … #define _CURSOR_POS_Y_MASK … #define _CURSOR_SIGN_Y_SHIFT … #define _CURSOR_SIGN_Y_MASK … #define _SPRITE_FMT_SHIFT … #define _SPRITE_COLOR_ORDER_SHIFT … #define _SPRITE_YUV_ORDER_SHIFT … #define _SPRITE_STRIDE_SHIFT … #define _SPRITE_STRIDE_MASK … #define _SPRITE_SIZE_WIDTH_SHIFT … #define _SPRITE_SIZE_HEIGHT_SHIFT … #define _SPRITE_SIZE_WIDTH_MASK … #define _SPRITE_SIZE_HEIGHT_MASK … #define _SPRITE_POS_X_SHIFT … #define _SPRITE_POS_Y_SHIFT … #define _SPRITE_POS_X_MASK … #define _SPRITE_POS_Y_MASK … #define _SPRITE_OFFSET_START_X_SHIFT … #define _SPRITE_OFFSET_START_Y_SHIFT … #define _SPRITE_OFFSET_START_X_MASK … #define _SPRITE_OFFSET_START_Y_MASK … enum GVT_FB_EVENT { … }; enum DDI_PORT { … }; /* color space conversion and gamma correction are not included */ struct intel_vgpu_primary_plane_format { … }; struct intel_vgpu_sprite_plane_format { … }; struct intel_vgpu_cursor_plane_format { … }; int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, struct intel_vgpu_primary_plane_format *plane); int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, struct intel_vgpu_cursor_plane_format *plane); int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, struct intel_vgpu_sprite_plane_format *plane); #endif
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