/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Kevin Tian <[email protected]> * Eddie Dong <[email protected]> * * Contributors: * Niu Bing <[email protected]> * Zhi Wang <[email protected]> * */ #ifndef _GVT_H_ #define _GVT_H_ #include <uapi/linux/pci_regs.h> #include <linux/vfio.h> #include <linux/mdev.h> #include <asm/kvm_page_track.h> #include "gt/intel_gt.h" #include "intel_gvt.h" #include "debug.h" #include "mmio.h" #include "reg.h" #include "interrupt.h" #include "gtt.h" #include "display.h" #include "edid.h" #include "execlist.h" #include "scheduler.h" #include "sched_policy.h" #include "mmio_context.h" #include "cmd_parser.h" #include "fb_decoder.h" #include "dmabuf.h" #include "page_track.h" #define GVT_MAX_VGPU … struct engine_mmio; /* Describe per-platform limitations. */ struct intel_gvt_device_info { … }; /* GM resources owned by a vGPU */ struct intel_vgpu_gm { … }; #define INTEL_GVT_MAX_NUM_FENCES … /* Fences owned by a vGPU */ struct intel_vgpu_fence { … }; struct intel_vgpu_mmio { … }; #define INTEL_GVT_MAX_BAR_NUM … struct intel_vgpu_pci_bar { … }; struct intel_vgpu_cfg_space { … }; #define vgpu_cfg_space(vgpu) … struct intel_vgpu_irq { … }; struct intel_vgpu_opregion { … }; #define vgpu_opregion(vgpu) … struct intel_vgpu_display { … }; struct vgpu_sched_ctl { … }; enum { … }; struct intel_vgpu_submission_ops { … }; struct intel_vgpu_submission { … }; #define KVMGT_DEBUGFS_FILENAME … enum { … }; struct intel_vgpu { … }; /* validating GM healthy status*/ #define vgpu_is_vm_unhealthy(ret_val) … struct intel_gvt_gm { … }; struct intel_gvt_fence { … }; /* Special MMIO blocks. */ struct gvt_mmio_block { … }; #define INTEL_GVT_MMIO_HASH_BITS … struct intel_gvt_mmio { … }; struct intel_gvt_firmware { … }; struct intel_vgpu_config { … }; struct intel_vgpu_type { … }; struct intel_gvt { … }; enum { … }; static inline void intel_gvt_request_service(struct intel_gvt *gvt, int service) { … } void intel_gvt_free_firmware(struct intel_gvt *gvt); int intel_gvt_load_firmware(struct intel_gvt *gvt); /* Aperture/GM space definitions for GVT device */ #define MB_TO_BYTES(mb) … #define BYTES_TO_MB(b) … #define HOST_LOW_GM_SIZE … #define HOST_HIGH_GM_SIZE … #define HOST_FENCE … #define gvt_to_ggtt(gvt) … /* Aperture/GM space definitions for GVT device */ #define gvt_aperture_sz(gvt) … #define gvt_aperture_pa_base(gvt) … #define gvt_ggtt_gm_sz(gvt) … #define gvt_ggtt_sz(gvt) … #define gvt_hidden_sz(gvt) … #define gvt_aperture_gmadr_base(gvt) … #define gvt_aperture_gmadr_end(gvt) … #define gvt_hidden_gmadr_base(gvt) … #define gvt_hidden_gmadr_end(gvt) … #define gvt_fence_sz(gvt) … /* Aperture/GM space definitions for vGPU */ #define vgpu_aperture_offset(vgpu) … #define vgpu_hidden_offset(vgpu) … #define vgpu_aperture_sz(vgpu) … #define vgpu_hidden_sz(vgpu) … #define vgpu_aperture_pa_base(vgpu) … #define vgpu_ggtt_gm_sz(vgpu) … #define vgpu_aperture_pa_end(vgpu) … #define vgpu_aperture_gmadr_base(vgpu) … #define vgpu_aperture_gmadr_end(vgpu) … #define vgpu_hidden_gmadr_base(vgpu) … #define vgpu_hidden_gmadr_end(vgpu) … #define vgpu_fence_sz(vgpu) … /* ring context size i.e. the first 0x50 dwords*/ #define RING_CTX_SIZE … int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, const struct intel_vgpu_config *conf); void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); void intel_vgpu_free_resource(struct intel_vgpu *vgpu); void intel_vgpu_write_fence(struct intel_vgpu *vgpu, u32 fence, u64 value); /* Macros for easily accessing vGPU virtual/shadow register. Explicitly seperate use for typed MMIO reg or real offset.*/ #define vgpu_vreg_t(vgpu, reg) … #define vgpu_vreg(vgpu, offset) … #define vgpu_vreg64_t(vgpu, reg) … #define vgpu_vreg64(vgpu, offset) … #define for_each_active_vgpu(gvt, vgpu, id) … static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, u32 offset, u32 val, bool low) { … } int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); int intel_gvt_create_vgpu(struct intel_vgpu *vgpu, const struct intel_vgpu_config *conf); void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, intel_engine_mask_t engine_mask); void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); int intel_gvt_set_opregion(struct intel_vgpu *vgpu); int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num); /* validating GM functions */ #define vgpu_gmadr_is_aperture(vgpu, gmadr) … #define vgpu_gmadr_is_hidden(vgpu, gmadr) … #define vgpu_gmadr_is_valid(vgpu, gmadr) … #define gvt_gmadr_is_aperture(gvt, gmadr) … #define gvt_gmadr_is_hidden(gvt, gmadr) … #define gvt_gmadr_is_valid(gvt, gmadr) … bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, unsigned long *h_index); int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, unsigned long *g_index); void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, bool primary); void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) { … } void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); void populate_pvinfo_page(struct intel_vgpu *vgpu); int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); void intel_vgpu_detach_regions(struct intel_vgpu *vgpu); enum { … }; static inline void mmio_hw_access_pre(struct intel_gt *gt) { … } static inline void mmio_hw_access_post(struct intel_gt *gt) { … } /** * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed * @gvt: a GVT device * @offset: register offset * */ static inline void intel_gvt_mmio_set_accessed( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command * @gvt: a GVT device * @offset: register offset * * Returns: * True if an MMIO is able to be accessed by GPU commands */ static inline bool intel_gvt_mmio_is_cmd_accessible( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_set_cmd_accessible - * mark a MMIO could be accessible by command * @gvt: a GVT device * @offset: register offset * */ static inline void intel_gvt_mmio_set_cmd_accessible( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned * @gvt: a GVT device * @offset: register offset * */ static inline bool intel_gvt_mmio_is_unalign( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask * @gvt: a GVT device * @offset: register offset * * Returns: * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. * */ static inline bool intel_gvt_mmio_has_mode_mask( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_is_sr_in_ctx - * check if an MMIO has F_SR_IN_CTX mask * @gvt: a GVT device * @offset: register offset * * Returns: * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't. * */ static inline bool intel_gvt_mmio_is_sr_in_ctx( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_set_sr_in_ctx - * mask an MMIO in GVT's mmio save-restore list and also * in hardware logical context image * @gvt: a GVT device * @offset: register offset * */ static inline void intel_gvt_mmio_set_sr_in_ctx( struct intel_gvt *gvt, unsigned int offset) { … } void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); /** * intel_gvt_mmio_set_cmd_write_patch - * mark an MMIO if its cmd write needs to be * patched * @gvt: a GVT device * @offset: register offset * */ static inline void intel_gvt_mmio_set_cmd_write_patch( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to * be patched * @gvt: a GVT device * @offset: register offset * * Returns: * True if GPU commmand write to an MMIO should be patched */ static inline bool intel_gvt_mmio_is_cmd_write_patch( struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_read_gpa - copy data from GPA to host data buffer * @vgpu: a vGPU * @gpa: guest physical address * @buf: host data buffer * @len: data length * * Returns: * Zero on success, negative error code if failed. */ static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa, void *buf, unsigned long len) { … } /** * intel_gvt_write_gpa - copy data from host data buffer to GPA * @vgpu: a vGPU * @gpa: guest physical address * @buf: host data buffer * @len: data length * * Returns: * Zero on success, negative error code if failed. */ static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu, unsigned long gpa, void *buf, unsigned long len) { … } void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); void intel_gvt_debugfs_init(struct intel_gvt *gvt); void intel_gvt_debugfs_clean(struct intel_gvt *gvt); int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn); int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn); int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr); int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, unsigned long size, dma_addr_t *dma_addr); void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr); #include "trace.h" #endif
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