/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Ke Yu * Kevin Tian <[email protected]> * Zhiyuan Lv <[email protected]> * * Contributors: * Min He <[email protected]> * Ping Gao <[email protected]> * Tina Zhang <[email protected]> * Yulei Zhang <[email protected]> * Zhi Wang <[email protected]> * */ #include <linux/slab.h> #include "i915_drv.h" #include "i915_reg.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gpu_commands.h" #include "gt/intel_gt_regs.h" #include "gt/intel_lrc.h" #include "gt/intel_ring.h" #include "gt/intel_gt_requests.h" #include "gt/shmem_utils.h" #include "gvt.h" #include "i915_pvinfo.h" #include "trace.h" #include "display/i9xx_plane_regs.h" #include "display/intel_display.h" #include "display/intel_sprite_regs.h" #include "gem/i915_gem_context.h" #include "gem/i915_gem_pm.h" #include "gt/intel_context.h" #define INVALID_OP … #define OP_LEN_MI … #define OP_LEN_2D … #define OP_LEN_3D_MEDIA … #define OP_LEN_MFX_VC … #define OP_LEN_VEBOX … #define CMD_TYPE(cmd) … struct sub_op_bits { … }; struct decode_info { … }; #define MAX_CMD_BUDGET … #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING … #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING … #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING … #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING … #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING … #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING … /* Render Command Map */ /* MI_* command Opcode (28:23) */ #define OP_MI_NOOP … #define OP_MI_SET_PREDICATE … #define OP_MI_USER_INTERRUPT … #define OP_MI_WAIT_FOR_EVENT … #define OP_MI_FLUSH … #define OP_MI_ARB_CHECK … #define OP_MI_RS_CONTROL … #define OP_MI_REPORT_HEAD … #define OP_MI_ARB_ON_OFF … #define OP_MI_URB_ATOMIC_ALLOC … #define OP_MI_BATCH_BUFFER_END … #define OP_MI_SUSPEND_FLUSH … #define OP_MI_PREDICATE … #define OP_MI_TOPOLOGY_FILTER … #define OP_MI_SET_APPID … #define OP_MI_RS_CONTEXT … #define OP_MI_LOAD_SCAN_LINES_INCL … #define OP_MI_DISPLAY_FLIP … #define OP_MI_SEMAPHORE_MBOX … #define OP_MI_SET_CONTEXT … #define OP_MI_MATH … #define OP_MI_URB_CLEAR … #define OP_MI_SEMAPHORE_SIGNAL … #define OP_MI_SEMAPHORE_WAIT … #define OP_MI_STORE_DATA_IMM … #define OP_MI_STORE_DATA_INDEX … #define OP_MI_LOAD_REGISTER_IMM … #define OP_MI_UPDATE_GTT … #define OP_MI_STORE_REGISTER_MEM … #define OP_MI_FLUSH_DW … #define OP_MI_CLFLUSH … #define OP_MI_REPORT_PERF_COUNT … #define OP_MI_LOAD_REGISTER_MEM … #define OP_MI_LOAD_REGISTER_REG … #define OP_MI_RS_STORE_DATA_IMM … #define OP_MI_LOAD_URB_MEM … #define OP_MI_STORE_URM_MEM … #define OP_MI_2E … #define OP_MI_2F … #define OP_MI_BATCH_BUFFER_START … /* Bit definition for dword 0 */ #define _CMDBIT_BB_START_IN_PPGTT … #define OP_MI_CONDITIONAL_BATCH_BUFFER_END … #define BATCH_BUFFER_ADDR_MASK … #define BATCH_BUFFER_ADDR_HIGH_MASK … #define BATCH_BUFFER_ADR_SPACE_BIT(x) … #define BATCH_BUFFER_2ND_LEVEL_BIT(x) … /* 2D command: Opcode (28:22) */ #define OP_2D(x) … #define OP_XY_SETUP_BLT … #define OP_XY_SETUP_CLIP_BLT … #define OP_XY_SETUP_MONO_PATTERN_SL_BLT … #define OP_XY_PIXEL_BLT … #define OP_XY_SCANLINES_BLT … #define OP_XY_TEXT_BLT … #define OP_XY_TEXT_IMMEDIATE_BLT … #define OP_XY_COLOR_BLT … #define OP_XY_PAT_BLT … #define OP_XY_MONO_PAT_BLT … #define OP_XY_SRC_COPY_BLT … #define OP_XY_MONO_SRC_COPY_BLT … #define OP_XY_FULL_BLT … #define OP_XY_FULL_MONO_SRC_BLT … #define OP_XY_FULL_MONO_PATTERN_BLT … #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT … #define OP_XY_MONO_PAT_FIXED_BLT … #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT … #define OP_XY_PAT_BLT_IMMEDIATE … #define OP_XY_SRC_COPY_CHROMA_BLT … #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT … #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT … #define OP_XY_PAT_CHROMA_BLT … #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE … /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */ #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) … #define OP_STATE_PREFETCH … #define OP_STATE_BASE_ADDRESS … #define OP_STATE_SIP … #define OP_3D_MEDIA_0_1_4 … #define OP_SWTESS_BASE_ADDRESS … #define OP_3DSTATE_VF_STATISTICS_GM45 … #define OP_PIPELINE_SELECT … #define OP_MEDIA_VFE_STATE … #define OP_MEDIA_CURBE_LOAD … #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD … #define OP_MEDIA_GATEWAY_STATE … #define OP_MEDIA_STATE_FLUSH … #define OP_MEDIA_POOL_STATE … #define OP_MEDIA_OBJECT … #define OP_MEDIA_OBJECT_PRT … #define OP_MEDIA_OBJECT_WALKER … #define OP_GPGPU_WALKER … #define OP_3DSTATE_CLEAR_PARAMS … #define OP_3DSTATE_DEPTH_BUFFER … #define OP_3DSTATE_STENCIL_BUFFER … #define OP_3DSTATE_HIER_DEPTH_BUFFER … #define OP_3DSTATE_VERTEX_BUFFERS … #define OP_3DSTATE_VERTEX_ELEMENTS … #define OP_3DSTATE_INDEX_BUFFER … #define OP_3DSTATE_VF_STATISTICS … #define OP_3DSTATE_VF … #define OP_3DSTATE_CC_STATE_POINTERS … #define OP_3DSTATE_SCISSOR_STATE_POINTERS … #define OP_3DSTATE_VS … #define OP_3DSTATE_GS … #define OP_3DSTATE_CLIP … #define OP_3DSTATE_SF … #define OP_3DSTATE_WM … #define OP_3DSTATE_CONSTANT_VS … #define OP_3DSTATE_CONSTANT_GS … #define OP_3DSTATE_CONSTANT_PS … #define OP_3DSTATE_SAMPLE_MASK … #define OP_3DSTATE_CONSTANT_HS … #define OP_3DSTATE_CONSTANT_DS … #define OP_3DSTATE_HS … #define OP_3DSTATE_TE … #define OP_3DSTATE_DS … #define OP_3DSTATE_STREAMOUT … #define OP_3DSTATE_SBE … #define OP_3DSTATE_PS … #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP … #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC … #define OP_3DSTATE_BLEND_STATE_POINTERS … #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS … #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS … #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS … #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS … #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS … #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS … #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS … #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS … #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS … #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS … #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS … #define OP_3DSTATE_URB_VS … #define OP_3DSTATE_URB_HS … #define OP_3DSTATE_URB_DS … #define OP_3DSTATE_URB_GS … #define OP_3DSTATE_GATHER_CONSTANT_VS … #define OP_3DSTATE_GATHER_CONSTANT_GS … #define OP_3DSTATE_GATHER_CONSTANT_HS … #define OP_3DSTATE_GATHER_CONSTANT_DS … #define OP_3DSTATE_GATHER_CONSTANT_PS … #define OP_3DSTATE_DX9_CONSTANTF_VS … #define OP_3DSTATE_DX9_CONSTANTF_PS … #define OP_3DSTATE_DX9_CONSTANTI_VS … #define OP_3DSTATE_DX9_CONSTANTI_PS … #define OP_3DSTATE_DX9_CONSTANTB_VS … #define OP_3DSTATE_DX9_CONSTANTB_PS … #define OP_3DSTATE_DX9_LOCAL_VALID_VS … #define OP_3DSTATE_DX9_LOCAL_VALID_PS … #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS … #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS … #define OP_3DSTATE_BINDING_TABLE_EDIT_VS … #define OP_3DSTATE_BINDING_TABLE_EDIT_GS … #define OP_3DSTATE_BINDING_TABLE_EDIT_HS … #define OP_3DSTATE_BINDING_TABLE_EDIT_DS … #define OP_3DSTATE_BINDING_TABLE_EDIT_PS … #define OP_3DSTATE_VF_INSTANCING … #define OP_3DSTATE_VF_SGVS … #define OP_3DSTATE_VF_TOPOLOGY … #define OP_3DSTATE_WM_CHROMAKEY … #define OP_3DSTATE_PS_BLEND … #define OP_3DSTATE_WM_DEPTH_STENCIL … #define OP_3DSTATE_PS_EXTRA … #define OP_3DSTATE_RASTER … #define OP_3DSTATE_SBE_SWIZ … #define OP_3DSTATE_WM_HZ_OP … #define OP_3DSTATE_COMPONENT_PACKING … #define OP_3DSTATE_DRAWING_RECTANGLE … #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 … #define OP_3DSTATE_CHROMA_KEY … #define OP_SNB_3DSTATE_DEPTH_BUFFER … #define OP_3DSTATE_POLY_STIPPLE_OFFSET … #define OP_3DSTATE_POLY_STIPPLE_PATTERN … #define OP_3DSTATE_LINE_STIPPLE … #define OP_3DSTATE_AA_LINE_PARAMS … #define OP_3DSTATE_GS_SVB_INDEX … #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 … #define OP_3DSTATE_MULTISAMPLE_BDW … #define OP_SNB_3DSTATE_STENCIL_BUFFER … #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER … #define OP_SNB_3DSTATE_CLEAR_PARAMS … #define OP_3DSTATE_MONOFILTER_SIZE … #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS … #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS … #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS … #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS … #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS … #define OP_3DSTATE_SO_DECL_LIST … #define OP_3DSTATE_SO_BUFFER … #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC … #define OP_3DSTATE_GATHER_POOL_ALLOC … #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC … #define OP_3DSTATE_SAMPLE_PATTERN … #define OP_PIPE_CONTROL … #define OP_3DPRIMITIVE … /* VCCP Command Parser */ /* * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License) * git://anongit.freedesktop.org/vaapi/intel-driver * src/i965_defines.h * */ #define OP_MFX(pipeline, op, sub_opa, sub_opb) … #define OP_MFX_PIPE_MODE_SELECT … #define OP_MFX_SURFACE_STATE … #define OP_MFX_PIPE_BUF_ADDR_STATE … #define OP_MFX_IND_OBJ_BASE_ADDR_STATE … #define OP_MFX_BSP_BUF_BASE_ADDR_STATE … #define OP_2_0_0_5 … #define OP_MFX_STATE_POINTER … #define OP_MFX_QM_STATE … #define OP_MFX_FQM_STATE … #define OP_MFX_PAK_INSERT_OBJECT … #define OP_MFX_STITCH_OBJECT … #define OP_MFD_IT_OBJECT … #define OP_MFX_WAIT … #define OP_MFX_AVC_IMG_STATE … #define OP_MFX_AVC_QM_STATE … #define OP_MFX_AVC_DIRECTMODE_STATE … #define OP_MFX_AVC_SLICE_STATE … #define OP_MFX_AVC_REF_IDX_STATE … #define OP_MFX_AVC_WEIGHTOFFSET_STATE … #define OP_MFD_AVC_PICID_STATE … #define OP_MFD_AVC_DPB_STATE … #define OP_MFD_AVC_SLICEADDR … #define OP_MFD_AVC_BSD_OBJECT … #define OP_MFC_AVC_PAK_OBJECT … #define OP_MFX_VC1_PRED_PIPE_STATE … #define OP_MFX_VC1_DIRECTMODE_STATE … #define OP_MFD_VC1_SHORT_PIC_STATE … #define OP_MFD_VC1_LONG_PIC_STATE … #define OP_MFD_VC1_BSD_OBJECT … #define OP_MFX_MPEG2_PIC_STATE … #define OP_MFX_MPEG2_QM_STATE … #define OP_MFD_MPEG2_BSD_OBJECT … #define OP_MFC_MPEG2_SLICEGROUP_STATE … #define OP_MFC_MPEG2_PAK_OBJECT … #define OP_MFX_2_6_0_0 … #define OP_MFX_2_6_0_8 … #define OP_MFX_2_6_0_9 … #define OP_MFX_JPEG_PIC_STATE … #define OP_MFX_JPEG_HUFF_TABLE_STATE … #define OP_MFD_JPEG_BSD_OBJECT … #define OP_VEB(pipeline, op, sub_opa, sub_opb) … #define OP_VEB_SURFACE_STATE … #define OP_VEB_STATE … #define OP_VEB_DNDI_IECP_STATE … struct parser_exec_state; parser_cmd_handler; #define GVT_CMD_HASH_BITS … /* which DWords need address fix */ #define ADDR_FIX_1(x1) … #define ADDR_FIX_2(x1, x2) … #define ADDR_FIX_3(x1, x2, x3) … #define ADDR_FIX_4(x1, x2, x3, x4) … #define ADDR_FIX_5(x1, x2, x3, x4, x5) … #define DWORD_FIELD(dword, end, start) … #define OP_LENGTH_BIAS … #define CMD_LEN(value) … static int gvt_check_valid_cmd_length(int len, int valid_len) { … } struct cmd_info { … }; struct cmd_entry { … }; enum { … }; enum { … }; struct parser_exec_state { … }; #define gmadr_dw_number(s) … static unsigned long bypass_scan_mask = …; /* ring ALL, type = 0 */ static const struct sub_op_bits sub_op_mi[] = …; static const struct decode_info decode_info_mi = …; /* ring RCS, command type 2 */ static const struct sub_op_bits sub_op_2d[] = …; static const struct decode_info decode_info_2d = …; /* ring RCS, command type 3 */ static const struct sub_op_bits sub_op_3d_media[] = …; static const struct decode_info decode_info_3d_media = …; /* ring VCS, command type 3 */ static const struct sub_op_bits sub_op_mfx_vc[] = …; static const struct decode_info decode_info_mfx_vc = …; /* ring VECS, command type 3 */ static const struct sub_op_bits sub_op_vebox[] = …; static const struct decode_info decode_info_vebox = …; static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = …; static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine) { … } static inline const struct cmd_info * find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode, const struct intel_engine_cs *engine) { … } static inline const struct cmd_info * get_cmd_info(struct intel_gvt *gvt, u32 cmd, const struct intel_engine_cs *engine) { … } static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) { … } static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine) { … } static inline u32 *cmd_ptr(struct parser_exec_state *s, int index) { … } static inline u32 cmd_val(struct parser_exec_state *s, int index) { … } static inline bool is_init_ctx(struct parser_exec_state *s) { … } static void parser_exec_state_dump(struct parser_exec_state *s) { … } static inline void update_ip_va(struct parser_exec_state *s) { … } static inline int ip_gma_set(struct parser_exec_state *s, unsigned long ip_gma) { … } static inline int ip_gma_advance(struct parser_exec_state *s, unsigned int dw_len) { … } static inline int get_cmd_length(const struct cmd_info *info, u32 cmd) { … } static inline int cmd_length(struct parser_exec_state *s) { … } /* do not remove this, some platform may need clflush here */ #define patch_value(s, addr, val) … static inline bool is_mocs_mmio(unsigned int offset) { … } static int is_cmd_update_pdps(unsigned int offset, struct parser_exec_state *s) { … } static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s, unsigned int offset, unsigned int index) { … } static int cmd_reg_handler(struct parser_exec_state *s, unsigned int offset, unsigned int index, char *cmd) { … } #define cmd_reg(s, i) … #define cmd_reg_inhibit(s, i) … #define cmd_gma(s, i) … #define cmd_gma_hi(s, i) … static int cmd_handler_lri(struct parser_exec_state *s) { … } static int cmd_handler_lrr(struct parser_exec_state *s) { … } static inline int cmd_address_audit(struct parser_exec_state *s, unsigned long guest_gma, int op_size, bool index_mode); static int cmd_handler_lrm(struct parser_exec_state *s) { … } static int cmd_handler_srm(struct parser_exec_state *s) { … } struct cmd_interrupt_event { … }; static const struct cmd_interrupt_event cmd_interrupt_events[] = …; static int cmd_handler_pipe_control(struct parser_exec_state *s) { … } static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) { … } static int cmd_advance_default(struct parser_exec_state *s) { … } static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s) { … } struct mi_display_flip_command_info { … }; struct plane_code_mapping { … }; static int gen8_decode_mi_display_flip(struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int skl_decode_mi_display_flip(struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int gen8_check_mi_display_flip(struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int gen8_update_plane_mmio_from_mi_display_flip( struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int decode_mi_display_flip(struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int check_mi_display_flip(struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int update_plane_mmio_from_mi_display_flip( struct parser_exec_state *s, struct mi_display_flip_command_info *info) { … } static int cmd_handler_mi_display_flip(struct parser_exec_state *s) { … } static bool is_wait_for_flip_pending(u32 cmd) { … } static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s) { … } static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index) { … } static inline int cmd_address_audit(struct parser_exec_state *s, unsigned long guest_gma, int op_size, bool index_mode) { … } static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) { … } static inline int unexpected_cmd(struct parser_exec_state *s) { … } static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s) { … } static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s) { … } static int cmd_handler_mi_op_2e(struct parser_exec_state *s) { … } static int cmd_handler_mi_op_2f(struct parser_exec_state *s) { … } static int cmd_handler_mi_store_data_index(struct parser_exec_state *s) { … } static int cmd_handler_mi_clflush(struct parser_exec_state *s) { … } static int cmd_handler_mi_conditional_batch_buffer_end( struct parser_exec_state *s) { … } static int cmd_handler_mi_update_gtt(struct parser_exec_state *s) { … } static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) { … } static void addr_type_update_snb(struct parser_exec_state *s) { … } static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, unsigned long gma, unsigned long end_gma, void *va) { … } /* * Check whether a batch buffer needs to be scanned. Currently * the only criteria is based on privilege. */ static int batch_buffer_needs_scan(struct parser_exec_state *s) { … } static const char *repr_addr_type(unsigned int type) { … } static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size, unsigned long *bb_end_cmd_offset) { … } static int audit_bb_end(struct parser_exec_state *s, void *va) { … } static int perform_bb_shadow(struct parser_exec_state *s) { … } static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) { … } static int mi_noop_index; static const struct cmd_info cmd_info[] = …; static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) { … } /* call the cmd handler, and advance ip */ static int cmd_parser_exec(struct parser_exec_state *s) { … } static inline bool gma_out_of_range(unsigned long gma, unsigned long gma_head, unsigned int gma_tail) { … } /* Keep the consistent return type, e.g EBADRQC for unknown * cmd, EFAULT for invalid address, EPERM for nonpriv. later * works as the input of VM healthy status. */ static int command_scan(struct parser_exec_state *s, unsigned long rb_head, unsigned long rb_tail, unsigned long rb_start, unsigned long rb_len) { … } static int scan_workload(struct intel_vgpu_workload *workload) { … } static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) { … } static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) { … } int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) { … } static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) { … } static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) { … } int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) { … } /* generate dummy contexts by sending empty requests to HW, and let * the HW to fill Engine Contexts. This dummy contexts are used for * initialization purpose (update reg whitelist), so referred to as * init context here */ void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu) { … } int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload) { … } static int init_cmd_table(struct intel_gvt *gvt) { … } static void clean_cmd_table(struct intel_gvt *gvt) { … } void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) { … } int intel_gvt_init_cmd_parser(struct intel_gvt *gvt) { … }
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