/* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Kevin Tian <[email protected]> * Eddie Dong <[email protected]> * Zhiyuan Lv <[email protected]> * * Contributors: * Min He <[email protected]> * Tina Zhang <[email protected]> * Pei Zhang <[email protected]> * Niu Bing <[email protected]> * Ping Gao <[email protected]> * Zhi Wang <[email protected]> * */ #include "i915_drv.h" #include "i915_reg.h" #include "gvt.h" #include "i915_pvinfo.h" #include "intel_mchbar_regs.h" #include "display/bxt_dpio_phy_regs.h" #include "display/i9xx_plane_regs.h" #include "display/intel_cursor_regs.h" #include "display/intel_display_types.h" #include "display/intel_dmc_regs.h" #include "display/intel_dp_aux_regs.h" #include "display/intel_dpio_phy.h" #include "display/intel_fbc.h" #include "display/intel_fdi_regs.h" #include "display/intel_pps_regs.h" #include "display/intel_psr_regs.h" #include "display/intel_sprite_regs.h" #include "display/skl_universal_plane_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" #include "gt/intel_gt_regs.h" #include <linux/vmalloc.h> /* XXX FIXME i915 has changed PP_XXX definition */ #define PCH_PP_STATUS … #define PCH_PP_CONTROL … #define PCH_PP_ON_DELAYS … #define PCH_PP_OFF_DELAYS … #define PCH_PP_DIVISOR … unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) { … } static bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device) { … } static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, unsigned int offset) { … } static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, u16 flags, u32 addr_mask, u32 ro_mask, u32 device, gvt_mmio_func read, gvt_mmio_func write) { … } /** * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine * @gvt: a GVT device * @offset: register offset * * Returns: * The engine containing the offset within its mmio page. */ const struct intel_engine_cs * intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) { … } #define offset_to_fence_num(offset) … #define fence_num_to_offset(num) … void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) { … } static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, unsigned int fence_num, void *p_data, unsigned int bytes) { … } static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, void *p_data, unsigned int bytes) { … } static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, void *p_data, unsigned int bytes) { … } #define CALC_MODE_MASK_REG(old, new) … static int mul_force_wake_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int transconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } /* * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on * setup_virtual_dp_monitor(). * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled * DPLL. Later guest driver may setup a different DPLLx when setting mode. * So the correct sequence to find DP stream clock is: * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. * Then Refresh rate then can be calculated based on follow equations: * Pixel clock = h_total * v_total * refresh_rate * stream clock = Pixel clock * ls_clk = DP bitrate * Link M/N = strm_clk / ls_clk */ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) { … } static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) { … } static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) { … } static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) { … } static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } /* sorted in ascending order */ static i915_reg_t force_nonpriv_white_list[] = …; /* a simple bsearch */ static inline bool in_whitelist(u32 reg) { … } static int force_nonpriv_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } #define FDI_LINK_TRAIN_PATTERN1 … #define FDI_LINK_TRAIN_PATTERN2 … static int fdi_auto_training_started(struct intel_vgpu *vgpu) { … } static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, enum pipe pipe, unsigned int train_pattern) { … } #define INVALID_INDEX … static unsigned int calc_index(unsigned int offset, i915_reg_t _start, i915_reg_t _next, i915_reg_t _end) { … } #define FDI_RX_CTL_TO_PIPE(offset) … #define FDI_TX_CTL_TO_PIPE(offset) … #define FDI_RX_IMR_TO_PIPE(offset) … static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } #define DP_TP_CTL_TO_PORT(offset) … static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } #define DSPSURF_TO_PIPE(dev_priv, offset) … static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } #define SPRSURF_TO_PIPE(offset) … static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int reg50080_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, unsigned int reg) { … } static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, unsigned int reg, int len, bool data_valid) { … } static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, u8 t) { … } #define OFFSET_TO_DP_AUX_PORT(offset) … #define dpy_is_valid_port(port) … static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, unsigned int sbi_offset) { … } static void write_virtual_sbi_register(struct intel_vgpu *vgpu, unsigned int offset, u32 value) { … } static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } #define _vgtif_reg(x) … static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) { … } static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) { … } static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int pf_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } /* * FixMe: * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing * these MI_BATCH_BUFFER. * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT * PML4 PTE: PAT(0) PCD(1) PWT(1). * The performance is still expected to be low, will need further improvement. */ static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int guc_status_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int mmio_read_from_hw(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int ring_reset_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } #define MMIO_F(reg, s, f, am, rm, d, r, w) … #define MMIO_DH(reg, d, r, w) … #define MMIO_DFH(reg, d, f, r, w) … #define MMIO_GM(reg, d, r, w) … #define MMIO_GM_RDR(reg, d, r, w) … #define MMIO_RO(reg, d, f, rm, r, w) … #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) … #define MMIO_RING_DFH(prefix, d, f, r, w) … #define MMIO_RING_GM(prefix, d, r, w) … #define MMIO_RING_GM_RDR(prefix, d, r, w) … #define MMIO_RING_RO(prefix, d, f, rm, r, w) … static int init_generic_mmio_info(struct intel_gvt *gvt) { … } static int init_bdw_mmio_info(struct intel_gvt *gvt) { … } static int init_skl_mmio_info(struct intel_gvt *gvt) { … } static int init_bxt_mmio_info(struct intel_gvt *gvt) { … } static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device * @gvt: GVT device * * This function is called at the driver unloading stage, to clean up the MMIO * information table of GVT device * */ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) { … } static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, u32 size) { … } static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, u32 offset, u32 size) { … } static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, u32 size) { … } static int init_mmio_info(struct intel_gvt *gvt) { … } static int init_mmio_block_handlers(struct intel_gvt *gvt) { … } /** * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device * @gvt: GVT device * * This function is called at the initialization stage, to setup the MMIO * information table for GVT device * * Returns: * zero on success, negative if failed. */ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) { … } /** * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio * @gvt: a GVT device * @handler: the handler * @data: private data given to handler * * Returns: * Zero on success, negative error code if failed. */ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), void *data) { … } /** * intel_vgpu_default_mmio_read - default MMIO read handler * @vgpu: a vGPU * @offset: access offset * @p_data: data return buffer * @bytes: access data length * * Returns: * Zero on success, negative error code if failed. */ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } /** * intel_vgpu_default_mmio_write() - default MMIO write handler * @vgpu: a vGPU * @offset: access offset * @p_data: write data buffer * @bytes: access data length * * Returns: * Zero on success, negative error code if failed. */ int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } /** * intel_vgpu_mask_mmio_write - write mask register * @vgpu: a vGPU * @offset: access offset * @p_data: write data buffer * @bytes: access data length * * Returns: * Zero on success, negative error code if failed. */ int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { … } /** * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be * force-nopriv register * * @gvt: a GVT device * @offset: register offset * * Returns: * True if the register is in force-nonpriv whitelist; * False if outside; */ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, unsigned int offset) { … } /** * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers * @vgpu: a vGPU * @offset: register offset * @pdata: data buffer * @bytes: data length * @is_read: read or write * * Returns: * Zero on success, negative error code if failed. */ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, void *pdata, unsigned int bytes, bool is_read) { … } void intel_gvt_restore_fence(struct intel_gvt *gvt) { … } static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) { … } void intel_gvt_restore_mmio(struct intel_gvt *gvt) { … }
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