/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _XE_MI_COMMANDS_H_ #define _XE_MI_COMMANDS_H_ #include "instructions/xe_instr_defs.h" /* * MI (Memory Interface) commands are supported by all GT engines. They * provide general memory operations and command streamer control. MI commands * have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction * header dword and a specific MI opcode in bits 28:23. */ #define MI_OPCODE … #define MI_SUBOPCODE … #define __MI_INSTR(opcode) … #define MI_NOOP … #define MI_USER_INTERRUPT … #define MI_ARB_CHECK … #define MI_ARB_ON_OFF … #define MI_ARB_ENABLE … #define MI_ARB_DISABLE … #define MI_BATCH_BUFFER_END … #define MI_TOPOLOGY_FILTER … #define MI_FORCE_WAKEUP … #define MI_STORE_DATA_IMM … #define MI_SDI_GGTT … #define MI_SDI_LEN_DW … #define MI_SDI_NUM_DW(x) … #define MI_SDI_NUM_QW(x) … #define MI_LOAD_REGISTER_IMM … #define MI_LRI_LRM_CS_MMIO … #define MI_LRI_MMIO_REMAP_EN … #define MI_LRI_NUM_REGS(x) … #define MI_LRI_FORCE_POSTED … #define MI_LRI_LEN(x) … #define MI_FLUSH_DW … #define MI_FLUSH_DW_STORE_INDEX … #define MI_INVALIDATE_TLB … #define MI_FLUSH_DW_CCS … #define MI_FLUSH_DW_OP_STOREDW … #define MI_FLUSH_DW_LEN_DW … #define MI_FLUSH_IMM_DW … #define MI_FLUSH_IMM_QW … #define MI_FLUSH_DW_USE_GTT … #define MI_LOAD_REGISTER_MEM … #define MI_LRM_USE_GGTT … #define MI_COPY_MEM_MEM … #define MI_COPY_MEM_MEM_SRC_GGTT … #define MI_COPY_MEM_MEM_DST_GGTT … #define MI_BATCH_BUFFER_START … #endif
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