/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _XE_GT_REGS_H_ #define _XE_GT_REGS_H_ #include "regs/xe_reg_defs.h" /* * The GSI register range [0x0 - 0x40000) is replicated at a higher offset * for the media GT. xe_mmio and xe_gt_mcr functions will automatically * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. */ #define MEDIA_GT_GSI_OFFSET … #define MEDIA_GT_GSI_LENGTH … /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ #define MTL_MIRROR_TARGET_WP1 … #define MTL_CAGF_MASK … #define MTL_CC_MASK … /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 … #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK … #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ … #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ … #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ … #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ … #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK … #define FORCEWAKE_ACK_MEDIA_VDBOX(n) … #define FORCEWAKE_ACK_MEDIA_VEBOX(n) … #define FORCEWAKE_ACK_RENDER … #define GMD_ID … #define GMD_ID_ARCH_MASK … #define GMD_ID_RELEASE_MASK … #define GMD_ID_REVID … #define FORCEWAKE_ACK_GSC … #define FORCEWAKE_ACK_GT_MTL … #define MCFG_MCR_SELECTOR … #define MTL_MCR_SELECTOR … #define SF_MCR_SELECTOR … #define MCR_SELECTOR … #define GAM_MCR_SELECTOR … #define MCR_MULTICAST … #define MCR_SLICE_MASK … #define MCR_SLICE(slice) … #define MCR_SUBSLICE_MASK … #define MCR_SUBSLICE(subslice) … #define MTL_MCR_GROUPID … #define MTL_MCR_INSTANCEID … #define PS_INVOCATION_COUNT … #define XELP_GLOBAL_MOCS(i) … #define XEHP_GLOBAL_MOCS(i) … #define LE_SSE_MASK … #define LE_SSE(value) … #define LE_COS_MASK … #define LE_COS(value) … #define LE_SCF_MASK … #define LE_SCF(value) … #define LE_PFM_MASK … #define LE_PFM(value) … #define LE_SCC_MASK … #define LE_SCC(value) … #define LE_RSC_MASK … #define LE_RSC(value) … #define LE_AOM_MASK … #define LE_AOM(value) … #define LE_LRUM_MASK … #define LE_LRUM(value) … #define LE_TGT_CACHE_MASK … #define LE_TGT_CACHE(value) … #define LE_CACHEABILITY_MASK … #define LE_CACHEABILITY(value) … #define STATELESS_COMPRESSION_CTRL … #define UNIFIED_COMPRESSION_FORMAT … #define XE2_GAMREQSTRM_CTRL … #define CG_DIS_CNTLBUS … #define CCS_AUX_INV … #define VD0_AUX_INV … #define VE0_AUX_INV … #define VE1_AUX_INV … #define AUX_INV … #define XE2_LMEM_CFG … #define XEHP_TILE_ADDR_RANGE(_idx) … #define XEHP_FLAT_CCS_BASE_ADDR … #define XEHP_FLAT_CCS_PTR … #define WM_CHICKEN3 … #define HIZ_PLANE_COMPRESSION_DIS … #define CHICKEN_RASTER_1 … #define DIS_SF_ROUND_NEAREST_EVEN … #define DIS_CLIP_NEGATIVE_BOUNDING_BOX … #define CHICKEN_RASTER_2 … #define TBIMR_FAST_CLIP … #define FF_MODE … #define DIS_TE_AUTOSTRIP … #define VS_HIT_MAX_VALUE_MASK … #define DIS_MESH_PARTIAL_AUTOSTRIP … #define DIS_MESH_AUTOSTRIP … #define VFLSKPD … #define DIS_PARTIAL_AUTOSTRIP … #define DIS_AUTOSTRIP … #define DIS_OVER_FETCH_CACHE … #define DIS_MULT_MISS_RD_SQUASH … #define FF_MODE2 … #define XEHP_FF_MODE2 … #define FF_MODE2_GS_TIMER_MASK … #define FF_MODE2_GS_TIMER_224 … #define FF_MODE2_TDS_TIMER_MASK … #define FF_MODE2_TDS_TIMER_128 … #define XEHPG_INSTDONE_GEOM_SVGUNIT … #define CACHE_MODE_1 … #define MSAA_OPTIMIZATION_REDUC_DISABLE … #define COMMON_SLICE_CHICKEN1 … #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST … #define HIZ_CHICKEN … #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE … #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE … #define XEHP_PSS_MODE2 … #define SCOREBOARD_STALL_FLUSH_CONTROL … #define XEHP_PSS_CHICKEN … #define FLSH_IGNORES_PSD … #define FD_END_COLLECT … #define SC_INSTDONE … #define SC_INSTDONE_EXTRA … #define SC_INSTDONE_EXTRA2 … #define XEHPG_SC_INSTDONE … #define XEHPG_SC_INSTDONE_EXTRA … #define XEHPG_SC_INSTDONE_EXTRA2 … #define COMMON_SLICE_CHICKEN4 … #define DISABLE_TDC_LOAD_BALANCING_CALC … #define COMMON_SLICE_CHICKEN3 … #define XEHP_COMMON_SLICE_CHICKEN3 … #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN … #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE … #define BLEND_EMB_FIX_DISABLE_IN_RCC … #define DISABLE_CPS_AWARE_COLOR_PIPE … #define XEHP_SLICE_COMMON_ECO_CHICKEN1 … #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE … #define XE2LPM_CCCHKNREG1 … #define VF_PREEMPTION … #define PREEMPTION_VERTEX_COUNT … #define VF_SCRATCHPAD … #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE … #define VFG_PREEMPTION_CHICKEN … #define POLYGON_TRIFAN_LINELOOP_DISABLE … #define SQCNT1 … #define XELPMP_SQCNT1 … #define SQCNT1_PMON_ENABLE … #define SQCNT1_OABPC … #define ENFORCE_RAR … #define XEHP_SQCM … #define EN_32B_ACCESS … #define XE2_FLAT_CCS_BASE_RANGE_LOWER … #define XE2_FLAT_CCS_ENABLE … #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK … #define XE2_FLAT_CCS_BASE_RANGE_UPPER … #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK … #define GSCPSMI_BASE … #define CCCHKNREG1 … #define L3CMPCTRL … #define ENCOMPPERFFIX … /* Fuse readout registers for GT */ #define XEHP_FUSE4 … #define CFEG_WMTP_DISABLE … #define CCS_EN_MASK … #define GT_L3_EXC_MASK … #define MIRROR_FUSE3 … #define XE2_NODE_ENABLE_MASK … #define L3BANK_PAIR_COUNT … #define XEHPC_GT_L3_MODE_MASK … #define XE2_GT_L3_MODE_MASK … #define L3BANK_MASK … #define XELP_GT_L3_MODE_MASK … /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ #define MAX_MSLICES … #define MEML3_EN_MASK … #define MIRROR_FUSE1 … #define XELP_EU_ENABLE … #define XELP_EU_MASK … #define XELP_GT_SLICE_ENABLE … #define XELP_GT_GEOMETRY_DSS_ENABLE … #define GT_VEBOX_VDBOX_DISABLE … #define GT_VEBOX_DISABLE_MASK … #define GT_VDBOX_DISABLE_MASK … #define XEHP_GT_COMPUTE_DSS_ENABLE … #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT … #define XE2_GT_COMPUTE_DSS_2 … #define XE2_GT_GEOMETRY_DSS_1 … #define XE2_GT_GEOMETRY_DSS_2 … #define GDRST … #define GRDOM_GUC … #define GRDOM_FULL … #define MISCCPCTL … #define DOP_CLOCK_GATE_RENDER_ENABLE … #define UNSLCGCTL9430 … #define MSQDUNIT_CLKGATE_DIS … #define UNSLICE_UNIT_LEVEL_CLKGATE … #define VFUNIT_CLKGATE_DIS … #define TSGUNIT_CLKGATE_DIS … #define CG3DDISCFEG_CLKGATE_DIS … #define GAMEDIA_CLKGATE_DIS … #define HSUNIT_CLKGATE_DIS … #define VSUNIT_CLKGATE_DIS … #define UNSLCGCTL9440 … #define GAMTLBOACS_CLKGATE_DIS … #define GAMTLBVDBOX5_CLKGATE_DIS … #define GAMTLBVDBOX6_CLKGATE_DIS … #define GAMTLBVDBOX3_CLKGATE_DIS … #define GAMTLBVDBOX4_CLKGATE_DIS … #define GAMTLBVDBOX7_CLKGATE_DIS … #define GAMTLBVDBOX2_CLKGATE_DIS … #define GAMTLBVDBOX0_CLKGATE_DIS … #define GAMTLBKCR_CLKGATE_DIS … #define GAMTLBGUC_CLKGATE_DIS … #define GAMTLBBLT_CLKGATE_DIS … #define GAMTLBVDBOX1_CLKGATE_DIS … #define UNSLCGCTL9444 … #define GAMTLBGFXA0_CLKGATE_DIS … #define GAMTLBGFXA1_CLKGATE_DIS … #define GAMTLBCOMPA0_CLKGATE_DIS … #define GAMTLBCOMPA1_CLKGATE_DIS … #define GAMTLBCOMPB0_CLKGATE_DIS … #define GAMTLBCOMPB1_CLKGATE_DIS … #define GAMTLBCOMPC0_CLKGATE_DIS … #define GAMTLBCOMPC1_CLKGATE_DIS … #define GAMTLBCOMPD0_CLKGATE_DIS … #define GAMTLBCOMPD1_CLKGATE_DIS … #define GAMTLBMERT_CLKGATE_DIS … #define GAMTLBVEBOX3_CLKGATE_DIS … #define GAMTLBVEBOX2_CLKGATE_DIS … #define GAMTLBVEBOX1_CLKGATE_DIS … #define GAMTLBVEBOX0_CLKGATE_DIS … #define LTCDD_CLKGATE_DIS … #define XEHP_SLICE_UNIT_LEVEL_CLKGATE … #define L3_CR2X_CLKGATE_DIS … #define L3_CLKGATE_DIS … #define NODEDSS_CLKGATE_DIS … #define MSCUNIT_CLKGATE_DIS … #define RCCUNIT_CLKGATE_DIS … #define SARBUNIT_CLKGATE_DIS … #define SBEUNIT_CLKGATE_DIS … #define UNSLICE_UNIT_LEVEL_CLKGATE2 … #define VSUNIT_CLKGATE2_DIS … #define SUBSLICE_UNIT_LEVEL_CLKGATE … #define DSS_ROUTER_CLKGATE_DIS … #define GWUNIT_CLKGATE_DIS … #define SUBSLICE_UNIT_LEVEL_CLKGATE2 … #define CPSSUNIT_CLKGATE_DIS … #define SSMCGCTL9530 … #define RTFUNIT_CLKGATE_DIS … #define DFR_RATIO_EN_AND_CHICKEN … #define DFR_DISABLE … #define RPNSWREQ … #define REQ_RATIO_MASK … #define RP_CONTROL … #define RPSWCTL_MASK … #define RPSWCTL_ENABLE … #define RPSWCTL_DISABLE … #define RC_CONTROL … #define RC_CTL_HW_ENABLE … #define RC_CTL_TO_MODE … #define RC_CTL_RC6_ENABLE … #define RC_STATE … #define RC_IDLE_HYSTERSIS … #define MEDIA_POWERGATE_IDLE_HYSTERESIS … #define RENDER_POWERGATE_IDLE_HYSTERESIS … #define PMINTRMSK … #define PMINTR_DISABLE_REDIRECT_TO_GUC … #define ARAT_EXPIRED_INTRMSK … #define FORCEWAKE_GT … #define POWERGATE_ENABLE … #define RENDER_POWERGATE_ENABLE … #define MEDIA_POWERGATE_ENABLE … #define VDN_HCP_POWERGATE_ENABLE(n) … #define VDN_MFXVDENC_POWERGATE_ENABLE(n) … #define CTC_MODE … #define CTC_SHIFT_PARAMETER_MASK … #define CTC_SOURCE_DIVIDE_LOGIC … #define FORCEWAKE_RENDER … #define FORCEWAKE_MEDIA_VDBOX(n) … #define FORCEWAKE_MEDIA_VEBOX(n) … #define FORCEWAKE_GSC … #define XEHPC_LNCFMISCCFGREG0 … #define XEHPC_OVRLSCCC … /* L3 Cache Control */ #define LNCFCMOCS_REG_COUNT … #define XELP_LNCFCMOCS(i) … #define XEHP_LNCFCMOCS(i) … #define L3_UPPER_LKUP_MASK … #define L3_UPPER_GLBGO_MASK … #define L3_UPPER_IDX_CACHEABILITY_MASK … #define L3_UPPER_IDX_SCC_MASK … #define L3_UPPER_IDX_ESC_MASK … #define L3_LKUP_MASK … #define L3_LKUP(value) … #define L3_GLBGO_MASK … #define L3_GLBGO(value) … #define L3_CACHEABILITY_MASK … #define L3_CACHEABILITY(value) … #define L3_SCC_MASK … #define L3_SCC(value) … #define L3_ESC_MASK … #define L3_ESC(value) … #define XEHP_L3NODEARBCFG … #define XEHP_LNESPARE … #define L3SQCREG2 … #define COMPMEMRD256BOVRFETCHEN … #define L3SQCREG3 … #define COMPPWOVERFETCHEN … #define SCRATCH3_LBCF … #define RWFLUSHALLEN … #define XEHP_L3SQCREG5 … #define L3_PWM_TIMER_INIT_VAL_MASK … #define XEHP_L3SCQREG7 … #define BLEND_FILL_CACHING_OPT_DIS … #define XEHPC_L3CLOS_MASK(i) … #define XE2_GLOBAL_INVAL … #define XE2LPM_L3SQCREG2 … #define XE2LPM_L3SQCREG3 … #define XE2LPM_SCRATCH3_LBCF … #define XE2LPM_L3SQCREG5 … #define XE2_TDF_CTRL … #define TRANSIENT_FLUSH_REQUEST … #define XEHP_MERT_MOD_CTRL … #define RENDER_MOD_CTRL … #define COMP_MOD_CTRL … #define XEHP_VDBX_MOD_CTRL … #define XELPMP_VDBX_MOD_CTRL … #define XEHP_VEBX_MOD_CTRL … #define XELPMP_VEBX_MOD_CTRL … #define FORCE_MISS_FTLB … #define XEHP_GAMSTLB_CTRL … #define CONTROL_BLOCK_CLKGATE_DIS … #define EGRESS_BLOCK_CLKGATE_DIS … #define TAG_BLOCK_CLKGATE_DIS … #define XEHP_GAMCNTRL_CTRL … #define INVALIDATION_BROADCAST_MODE_DIS … #define GLOBAL_INVALIDATION_MODE … #define LMEM_CFG … #define LMEM_EN … #define LMTT_DIR_PTR … #define HALF_SLICE_CHICKEN5 … #define DISABLE_SAMPLE_G_PERFORMANCE … #define SAMPLER_INSTDONE … #define ROW_INSTDONE … #define SAMPLER_MODE … #define ENABLE_SMALLPL … #define SC_DISABLE_POWER_OPTIMIZATION_EBB … #define SAMPLER_ENABLE_HEADLESS_MSG … #define INDIRECT_STATE_BASE_ADDR_OVERRIDE … #define HALF_SLICE_CHICKEN7 … #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA … #define CLEAR_OPTIMIZATION_DISABLE … #define CACHE_MODE_SS … #define DISABLE_ECC … #define ENABLE_PREFETCH_INTO_IC … #define ROW_CHICKEN4 … #define DISABLE_GRF_CLEAR … #define XEHP_DIS_BBL_SYSPIPE … #define DISABLE_TDL_PUSH … #define DIS_PICK_2ND_EU … #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX … #define THREAD_EX_ARB_MODE … #define THREAD_EX_ARB_MODE_RR_AFTER_DEP … #define ROW_CHICKEN3 … #define XE2_EUPEND_CHK_FLUSH_DIS … #define DIS_FIX_EOT1_FLUSH … #define TDL_TSL_CHICKEN … #define STK_ID_RESTRICT … #define SLM_WMTP_RESTORE … #define ROW_CHICKEN … #define UGM_BACKUP_MODE … #define MDQ_ARBITRATION_MODE … #define STALL_DOP_GATING_DISABLE … #define EARLY_EOT_DIS … #define ROW_CHICKEN2 … #define DISABLE_READ_SUPPRESSION … #define DISABLE_EARLY_READ … #define ENABLE_LARGE_GRF_MODE … #define PUSH_CONST_DEREF_HOLD_DIS … #define DISABLE_TDL_SVHS_GATING … #define DISABLE_DOP_GATING … #define RT_CTRL … #define DIS_NULL_QUERY … #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK … #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT … #define XEHP_HDC_CHICKEN0 … #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK … #define DIS_ATOMIC_CHAINING_TYPED_WRITES … #define LSC_CHICKEN_BIT_0 … #define DISABLE_D8_D16_COASLESCE … #define WR_REQ_CHAINING_DIS … #define TGM_WRITE_EOM_FORCE … #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT … #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE … #define LSC_CHICKEN_BIT_0_UDW … #define UGM_FRAGMENT_THRESHOLD_TO_3 … #define DIS_CHAIN_2XSIMD8 … #define XE2_ALLOC_DPA_STARVE_FIX_DIS … #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL … #define FORCE_SLM_FENCE_SCOPE_TO_TILE … #define FORCE_UGM_FENCE_SCOPE_TO_TILE … #define MAXREQS_PER_BANK … #define DISABLE_128B_EVICTION_COMMAND_UDW … #define SARB_CHICKEN1 … #define COMP_CKN_IN … #define RCU_MODE … #define RCU_MODE_FIXED_SLICE_CCS_MODE … #define RCU_MODE_CCS_ENABLE … /* * Total of 4 cslices, where each cslice is in the form: * [0-3] CCS ID * [4-6] RSVD * [7] Disabled */ #define CCS_MODE … #define CCS_MODE_CSLICE_0_3_MASK … #define CCS_MODE_CSLICE_MASK … #define CCS_MODE_CSLICE_WIDTH … #define CCS_MODE_CSLICE(cslice, ccs) … #define FORCEWAKE_ACK_GT … /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */ #define FORCEWAKE_KERNEL … #define FORCEWAKE_MT(bit) … #define FORCEWAKE_MT_MASK(bit) … #define MTL_MEDIA_PERF_LIMIT_REASONS … #define MTL_MEDIA_MC6 … #define GT_CORE_STATUS … #define RCN_MASK … #define GT_C0 … #define GT_C6 … #define GT_GFX_RC6_LOCKED … #define GT_GFX_RC6 … #define GT0_PERF_LIMIT_REASONS … #define GT0_PERF_LIMIT_REASONS_MASK … #define PROCHOT_MASK … #define THERMAL_LIMIT_MASK … #define RATL_MASK … #define VR_THERMALERT_MASK … #define VR_TDC_MASK … #define POWER_LIMIT_4_MASK … #define POWER_LIMIT_1_MASK … #define POWER_LIMIT_2_MASK … #define GT_PERF_STATUS … #define VOLTAGE_MASK … /* * Note: Interrupt registers 1900xx are VF accessible only until version 12.50. * On newer platforms, VFs are using memory-based interrupts instead. * However, for simplicity we keep this XE_REG_OPTION_VF tag intact. */ #define GT_INTR_DW(x) … #define INTR_GSC … #define INTR_GUC … #define INTR_MGUC … #define INTR_BCS8 … #define INTR_BCS(x) … #define INTR_CCS(x) … #define INTR_RCS0 … #define INTR_VECS(x) … #define INTR_VCS(x) … #define RENDER_COPY_INTR_ENABLE … #define VCS_VECS_INTR_ENABLE … #define GUC_SG_INTR_ENABLE … #define ENGINE1_MASK … #define ENGINE0_MASK … #define GPM_WGBOXPERF_INTR_ENABLE … #define GUNIT_GSC_INTR_ENABLE … #define CCS_RSVD_INTR_ENABLE … #define INTR_IDENTITY_REG(x) … #define INTR_DATA_VALID … #define INTR_ENGINE_INSTANCE(x) … #define INTR_ENGINE_CLASS(x) … #define INTR_ENGINE_INTR(x) … #define OTHER_GUC_INSTANCE … #define OTHER_GSC_HECI2_INSTANCE … #define OTHER_GSC_INSTANCE … #define IIR_REG_SELECTOR(x) … #define RCS0_RSVD_INTR_MASK … #define BCS_RSVD_INTR_MASK … #define VCS0_VCS1_INTR_MASK … #define VCS2_VCS3_INTR_MASK … #define VECS0_VECS1_INTR_MASK … #define HECI2_RSVD_INTR_MASK … #define GUC_SG_INTR_MASK … #define GPM_WGBOXPERF_INTR_MASK … #define GUNIT_GSC_INTR_MASK … #define CCS0_CCS1_INTR_MASK … #define CCS2_CCS3_INTR_MASK … #define XEHPC_BCS1_BCS2_INTR_MASK … #define XEHPC_BCS3_BCS4_INTR_MASK … #define XEHPC_BCS5_BCS6_INTR_MASK … #define XEHPC_BCS7_BCS8_INTR_MASK … #define GT_WAIT_SEMAPHORE_INTERRUPT … #define GT_CONTEXT_SWITCH_INTERRUPT … #define GSC_ER_COMPLETE … #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT … #define GT_CS_MASTER_ERROR_INTERRUPT … #define GT_RENDER_USER_INTERRUPT … #endif
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