/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _XE_GSC_REGS_H_ #define _XE_GSC_REGS_H_ #include <linux/compiler.h> #include <linux/types.h> #include "regs/xe_reg_defs.h" /* Definitions of GSC H/W registers, bits, etc */ #define MTL_GSC_HECI1_BASE … #define MTL_GSC_HECI2_BASE … #define HECI_H_CSR(base) … #define HECI_H_CSR_IE … #define HECI_H_CSR_IS … #define HECI_H_CSR_IG … #define HECI_H_CSR_RDY … #define HECI_H_CSR_RST … /* * The FWSTS register values are FW defined and can be different between * HECI1 and HECI2 */ #define HECI_FWSTS1(base) … #define HECI1_FWSTS1_CURRENT_STATE … #define HECI1_FWSTS1_CURRENT_STATE_RESET … #define HECI1_FWSTS1_PROXY_STATE_NORMAL … #define HECI1_FWSTS1_INIT_COMPLETE … #define HECI_FWSTS2(base) … #define HECI_FWSTS3(base) … #define HECI_FWSTS4(base) … #define HECI_FWSTS5(base) … #define HECI1_FWSTS5_HUC_AUTH_DONE … #define HECI_FWSTS6(base) … #define HECI_H_GS1(base) … #define HECI_H_GS1_ER_PREP … #define GSCI_TIMER_STATUS … #define GSCI_TIMER_STATUS_VALUE … #define GSCI_TIMER_STATUS_RESET_IN_PROGRESS … #define GSCI_TIMER_STATUS_TIMER_EXPIRED … #define GSCI_TIMER_STATUS_RESET_COMPLETE … #define GSCI_TIMER_STATUS_OUT_OF_RESET … #endif
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