/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef _XE_GUC_REGS_H_ #define _XE_GUC_REGS_H_ #include <linux/compiler.h> #include <linux/types.h> #include "regs/xe_reg_defs.h" /* Definitions of GuC H/W registers, bits, etc */ #define DIST_DBS_POPULATED … #define DOORBELLS_PER_SQIDI_MASK … #define SQIDIS_DOORBELL_EXIST_MASK … #define DRBREGL(x) … #define DRB_VALID … #define DRBREGU(x) … #define GTCR … #define GTCR_INVALIDATE … #define GUC_ARAT_C6DIS … #define GUC_STATUS … #define GS_AUTH_STATUS_MASK … #define GS_AUTH_STATUS_BAD … #define GS_AUTH_STATUS_GOOD … #define GS_MIA_MASK … #define GS_MIA_CORE_STATE … #define GS_MIA_HALT_REQUESTED … #define GS_MIA_ISR_ENTRY … #define GS_UKERNEL_MASK … #define GS_BOOTROM_MASK … #define GS_BOOTROM_RSA_FAILED … #define GS_BOOTROM_JUMP_PASSED … #define GS_MIA_IN_RESET … #define GUC_HEADER_INFO … #define GUC_WOPCM_SIZE … #define GUC_WOPCM_SIZE_MASK … #define GUC_WOPCM_SIZE_LOCKED … #define GUC_SHIM_CONTROL … #define GUC_MOCS_INDEX_MASK … #define GUC_SHIM_WC_ENABLE … #define GUC_ENABLE_MIA_CLOCK_GATING … #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA … #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA … #define GUC_MSGCH_ENABLE … #define GUC_ENABLE_MIA_CACHING … #define GUC_ENABLE_READ_CACHE_LOGIC … #define GUC_DISABLE_SRAM_INIT_TO_ZEROES … #define SOFT_SCRATCH(n) … #define SOFT_SCRATCH_COUNT … #define HUC_KERNEL_LOAD_INFO … #define HUC_LOAD_SUCCESSFUL … #define UOS_RSA_SCRATCH(i) … #define UOS_RSA_SCRATCH_COUNT … #define DMA_ADDR_0_LOW … #define DMA_ADDR_0_HIGH … #define DMA_ADDR_1_LOW … #define DMA_ADDR_1_HIGH … #define DMA_ADDR_SPACE_MASK … #define DMA_ADDRESS_SPACE_WOPCM … #define DMA_ADDRESS_SPACE_GGTT … #define DMA_COPY_SIZE … #define DMA_CTRL … #define HUC_UKERNEL … #define UOS_MOVE … #define START_DMA … #define DMA_GUC_WOPCM_OFFSET … #define GUC_WOPCM_OFFSET_SHIFT … #define GUC_WOPCM_OFFSET_MASK … #define HUC_LOADING_AGENT_GUC … #define GUC_WOPCM_OFFSET_VALID … #define GUC_MAX_IDLE_COUNT … #define GUC_SEND_INTERRUPT … #define GUC_SEND_TRIGGER … #define GUC_BCS_RCS_IER … #define GUC_VCS2_VCS1_IER … #define GUC_WD_VECS_IER … #define GUC_PM_P24C_IER … #define GUC_TLB_INV_CR … #define GUC_TLB_INV_CR_INVALIDATE … #define HUC_STATUS2 … #define HUC_FW_VERIFIED … #define GT_PM_CONFIG … #define GT_DOORBELL_ENABLE … #define GUC_HOST_INTERRUPT … #define VF_SW_FLAG(n) … #define VF_SW_FLAG_COUNT … #define MED_GUC_HOST_INTERRUPT … #define MED_VF_SW_FLAG(n) … #define MED_VF_SW_FLAG_COUNT … #define GUC_TLB_INV_CR … #define GUC_TLB_INV_CR_INVALIDATE … #define PVC_GUC_TLB_INV_DESC0 … #define PVC_GUC_TLB_INV_DESC0_VALID … #define PVC_GUC_TLB_INV_DESC1 … #define PVC_GUC_TLB_INV_DESC1_INVALIDATE … /* GuC Interrupt Vector */ #define GUC_INTR_GUC2HOST … #define GUC_INTR_EXEC_ERROR … #define GUC_INTR_DISPLAY_EVENT … #define GUC_INTR_SEM_SIG … #define GUC_INTR_IOMMU2GUC … #define GUC_INTR_DOORBELL_RANG … #define GUC_INTR_DMA_DONE … #define GUC_INTR_FATAL_ERROR … #define GUC_INTR_NOTIF_ERROR … #define GUC_INTR_SW_INT_6 … #define GUC_INTR_SW_INT_5 … #define GUC_INTR_SW_INT_4 … #define GUC_INTR_SW_INT_3 … #define GUC_INTR_SW_INT_2 … #define GUC_INTR_SW_INT_1 … #define GUC_INTR_SW_INT_0 … #define GUC_NUM_DOORBELLS … /* format of the HW-monitored doorbell cacheline */ struct guc_doorbell_info { … } __packed; #endif
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