linux/drivers/gpu/drm/xe/xe_pcode_api.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2022 Intel Corporation
 */

/* Internal to xe_pcode */

#include "regs/xe_reg_defs.h"

#define PCODE_MAILBOX …
#define PCODE_READY …
#define PCODE_MB_PARAM2 …
#define PCODE_MB_PARAM1 …
#define PCODE_MB_COMMAND …
#define PCODE_ERROR_MASK …
#define PCODE_SUCCESS …
#define PCODE_ILLEGAL_CMD …
#define PCODE_TIMEOUT …
#define PCODE_ILLEGAL_DATA …
#define PCODE_ILLEGAL_SUBCOMMAND …
#define PCODE_LOCKED …
#define PCODE_GT_RATIO_OUT_OF_RANGE …
#define PCODE_REJECTED …

#define PCODE_DATA0 …
#define PCODE_DATA1 …

/* Min Freq QOS Table */
#define PCODE_WRITE_MIN_FREQ_TABLE …
#define PCODE_READ_MIN_FREQ_TABLE …
#define PCODE_FREQ_RING_RATIO_SHIFT …

/* PCODE Init */
#define DGFX_PCODE_STATUS …
#define DGFX_GET_INIT_STATUS …
#define DGFX_INIT_STATUS_COMPLETE …

#define PCODE_POWER_SETUP …
#define POWER_SETUP_SUBCOMMAND_READ_I1 …
#define POWER_SETUP_SUBCOMMAND_WRITE_I1 …
#define POWER_SETUP_I1_WATTS …
#define POWER_SETUP_I1_SHIFT …
#define POWER_SETUP_I1_DATA_MASK …

#define PCODE_FREQUENCY_CONFIG …
/* Frequency Config Sub Commands (param1) */
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 …
#define PCODE_MBOX_FC_SC_READ_FUSED_PN …
/* Domain IDs (param2) */
#define PCODE_MBOX_DOMAIN_HBM …

struct pcode_err_decode { … };