/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _XE_MCHBAR_REGS_H_ #define _XE_MCHBAR_REGS_H_ #include "regs/xe_reg_defs.h" /* * MCHBAR mirror. * * This mirrors the MCHBAR MMIO space whose location is determined by * device 0 function 0's pci config register 0x44 or 0x48 and matches it in * every way. */ #define MCHBAR_MIRROR_BASE_SNB … #define PCU_CR_PACKAGE_POWER_SKU … #define PKG_TDP … #define PKG_MIN_PWR … #define PKG_MAX_PWR … #define PKG_MAX_WIN … #define PKG_MAX_WIN_X … #define PKG_MAX_WIN_Y … #define PCU_CR_PACKAGE_POWER_SKU_UNIT … #define PKG_PWR_UNIT … #define PKG_ENERGY_UNIT … #define PKG_TIME_UNIT … #define PCU_CR_PACKAGE_ENERGY_STATUS … #define PCU_CR_PACKAGE_RAPL_LIMIT … #define PKG_PWR_LIM_1 … #define PKG_PWR_LIM_1_EN … #define PKG_PWR_LIM_1_TIME … #define PKG_PWR_LIM_1_TIME_X … #define PKG_PWR_LIM_1_TIME_Y … #endif /* _XE_MCHBAR_REGS_H_ */
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