/* SPDX-License-Identifier: GPL-2.0-only * * Copyright © 2018-2020 Intel Corporation */ #ifndef __KMB_REGS_H__ #define __KMB_REGS_H__ /*************************************************************************** * LCD controller control register defines ***************************************************************************/ #define LCD_CONTROL … #define LCD_CTRL_PROGRESSIVE … #define LCD_CTRL_INTERLACED … #define LCD_CTRL_ENABLE … #define LCD_CTRL_VL1_ENABLE … #define LCD_CTRL_VL2_ENABLE … #define LCD_CTRL_GL1_ENABLE … #define LCD_CTRL_GL2_ENABLE … #define LCD_CTRL_ALPHA_BLEND_VL1 … #define LCD_CTRL_ALPHA_BLEND_VL2 … #define LCD_CTRL_ALPHA_BLEND_GL1 … #define LCD_CTRL_ALPHA_BLEND_GL2 … #define LCD_CTRL_ALPHA_TOP_VL1 … #define LCD_CTRL_ALPHA_TOP_VL2 … #define LCD_CTRL_ALPHA_TOP_GL1 … #define LCD_CTRL_ALPHA_TOP_GL2 … #define LCD_CTRL_ALPHA_MIDDLE_VL1 … #define LCD_CTRL_ALPHA_MIDDLE_VL2 … #define LCD_CTRL_ALPHA_MIDDLE_GL1 … #define LCD_CTRL_ALPHA_MIDDLE_GL2 … #define LCD_CTRL_ALPHA_BOTTOM_VL1 … #define LCD_CTRL_ALPHA_BOTTOM_VL2 … #define LCD_CTRL_ALPHA_BOTTOM_GL1 … #define LCD_CTRL_ALPHA_BOTTOM_GL2 … #define LCD_CTRL_TIM_GEN_ENABLE … #define LCD_CTRL_CONTINUOUS … #define LCD_CTRL_ONE_SHOT … #define LCD_CTRL_PWM0_EN … #define LCD_CTRL_PWM1_EN … #define LCD_CTRL_PWM2_EN … #define LCD_CTRL_OUTPUT_DISABLED … #define LCD_CTRL_OUTPUT_ENABLED … #define LCD_CTRL_BPORCH_ENABLE … #define LCD_CTRL_FPORCH_ENABLE … #define LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE … #define LCD_CTRL_PIPELINE_DMA … #define LCD_CTRL_VHSYNC_IDLE_LVL … #define LCD_CTRL_ALPHA_ALL … /* interrupts */ #define LCD_INT_STATUS … #define LCD_INT_EOF … #define LCD_INT_LINE_CMP … #define LCD_INT_VERT_COMP … #define LAYER0_DMA_DONE … #define LAYER0_DMA_IDLE … #define LAYER0_DMA_FIFO_OVERFLOW … #define LAYER0_DMA_FIFO_UNDERFLOW … #define LAYER0_DMA_CB_FIFO_OVERFLOW … #define LAYER0_DMA_CB_FIFO_UNDERFLOW … #define LAYER0_DMA_CR_FIFO_OVERFLOW … #define LAYER0_DMA_CR_FIFO_UNDERFLOW … #define LAYER1_DMA_DONE … #define LAYER1_DMA_IDLE … #define LAYER1_DMA_FIFO_OVERFLOW … #define LAYER1_DMA_FIFO_UNDERFLOW … #define LAYER1_DMA_CB_FIFO_OVERFLOW … #define LAYER1_DMA_CB_FIFO_UNDERFLOW … #define LAYER1_DMA_CR_FIFO_OVERFLOW … #define LAYER1_DMA_CR_FIFO_UNDERFLOW … #define LAYER2_DMA_DONE … #define LAYER2_DMA_IDLE … #define LAYER2_DMA_FIFO_OVERFLOW … #define LAYER2_DMA_FIFO_UNDERFLOW … #define LAYER3_DMA_DONE … #define LAYER3_DMA_IDLE … #define LAYER3_DMA_FIFO_OVERFLOW … #define LAYER3_DMA_FIFO_UNDERFLOW … #define LCD_INT_LAYER … #define LCD_INT_ENABLE … #define LCD_INT_CLEAR … #define LCD_LINE_COUNT … #define LCD_LINE_COMPARE … #define LCD_VSTATUS … /*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal * interval interrupt */ /* BITS 13 and 14 */ #define LCD_VSTATUS_COMPARE … #define LCD_VSTATUS_VERTICAL_STATUS_MASK … #define LCD_VSTATUS_COMPARE_VSYNC … #define LCD_VSTATUS_COMPARE_BACKPORCH … #define LCD_VSTATUS_COMPARE_ACTIVE … #define LCD_VSTATUS_COMPARE_FRONT_PORCH … #define LCD_SCREEN_WIDTH … #define LCD_SCREEN_HEIGHT … #define LCD_FIELD_INT_CFG … #define LCD_FIFO_FLUSH … #define LCD_BG_COLOUR_LS … #define LCD_BG_COLOUR_MS … #define LCD_RAM_CFG … /**************************************************************************** * LCD controller Layer config register ***************************************************************************/ #define LCD_LAYER0_CFG … #define LCD_LAYERn_CFG(N) … #define LCD_LAYER_SCALE_H … #define LCD_LAYER_SCALE_V … #define LCD_LAYER_SCALE_H_V … #define LCD_LAYER_CSC_EN … #define LCD_LAYER_ALPHA_STATIC … #define LCD_LAYER_ALPHA_EMBED … #define LCD_LAYER_ALPHA_COMBI … #define LCD_LAYER_ALPHA_DISABLED … /* RGB multiplied with alpha */ #define LCD_LAYER_ALPHA_PREMULT … #define LCD_LAYER_INVERT_COL … #define LCD_LAYER_TRANSPARENT_EN … #define LCD_LAYER_FORMAT_YCBCR444PLAN … #define LCD_LAYER_FORMAT_YCBCR422PLAN … #define LCD_LAYER_FORMAT_YCBCR420PLAN … #define LCD_LAYER_FORMAT_RGB888PLAN … #define LCD_LAYER_FORMAT_YCBCR444LIN … #define LCD_LAYER_FORMAT_YCBCR422LIN … #define LCD_LAYER_FORMAT_RGB888 … #define LCD_LAYER_FORMAT_RGBA8888 … #define LCD_LAYER_FORMAT_RGBX8888 … #define LCD_LAYER_FORMAT_RGB565 … #define LCD_LAYER_FORMAT_RGBA1555 … #define LCD_LAYER_FORMAT_XRGB1555 … #define LCD_LAYER_FORMAT_RGB444 … #define LCD_LAYER_FORMAT_RGBA4444 … #define LCD_LAYER_FORMAT_RGBX4444 … #define LCD_LAYER_FORMAT_RGB332 … #define LCD_LAYER_FORMAT_RGBA3328 … #define LCD_LAYER_FORMAT_RGBX3328 … #define LCD_LAYER_FORMAT_CLUT … #define LCD_LAYER_FORMAT_NV12 … #define LCD_LAYER_PLANAR_STORAGE … #define LCD_LAYER_8BPP … #define LCD_LAYER_16BPP … #define LCD_LAYER_24BPP … #define LCD_LAYER_32BPP … #define LCD_LAYER_Y_ORDER … #define LCD_LAYER_CRCB_ORDER … #define LCD_LAYER_BGR_ORDER … #define LCD_LAYER_LUT_2ENT … #define LCD_LAYER_LUT_4ENT … #define LCD_LAYER_LUT_16ENT … #define LCD_LAYER_NO_FLIP … #define LCD_LAYER_FLIP_V … #define LCD_LAYER_FLIP_H … #define LCD_LAYER_ROT_R90 … #define LCD_LAYER_ROT_L90 … #define LCD_LAYER_ROT_180 … #define LCD_LAYER_FIFO_00 … #define LCD_LAYER_FIFO_25 … #define LCD_LAYER_FIFO_50 … #define LCD_LAYER_FIFO_100 … #define LCD_LAYER_INTERLEAVE_DIS … #define LCD_LAYER_INTERLEAVE_V … #define LCD_LAYER_INTERLEAVE_H … #define LCD_LAYER_INTERLEAVE_CH … #define LCD_LAYER_INTERLEAVE_V_SUB … #define LCD_LAYER_INTERLEAVE_H_SUB … #define LCD_LAYER_INTERLEAVE_CH_SUB … #define LCD_LAYER_INTER_POS_EVEN … #define LCD_LAYER_INTER_POS_ODD … #define LCD_LAYER0_COL_START … #define LCD_LAYERn_COL_START(N) … #define LCD_LAYER0_ROW_START … #define LCD_LAYERn_ROW_START(N) … #define LCD_LAYER0_WIDTH … #define LCD_LAYERn_WIDTH(N) … #define LCD_LAYER0_HEIGHT … #define LCD_LAYERn_HEIGHT(N) … #define LCD_LAYER0_SCALE_CFG … #define LCD_LAYERn_SCALE_CFG(N) … #define LCD_LAYER0_ALPHA … #define LCD_LAYERn_ALPHA(N) … #define LCD_LAYER0_INV_COLOUR_LS … #define LCD_LAYERn_INV_COLOUR_LS(N) … #define LCD_LAYER0_INV_COLOUR_MS … #define LCD_LAYERn_INV_COLOUR_MS(N) … #define LCD_LAYER0_TRANS_COLOUR_LS … #define LCD_LAYERn_TRANS_COLOUR_LS(N) … #define LCD_LAYER0_TRANS_COLOUR_MS … #define LCD_LAYERn_TRANS_COLOUR_MS(N) … #define LCD_LAYER0_CSC_COEFF11 … #define LCD_LAYERn_CSC_COEFF11(N) … #define LCD_LAYER0_CSC_COEFF12 … #define LCD_LAYERn_CSC_COEFF12(N) … #define LCD_LAYER0_CSC_COEFF13 … #define LCD_LAYERn_CSC_COEFF13(N) … #define LCD_LAYER0_CSC_COEFF21 … #define LCD_LAYERn_CSC_COEFF21(N) … #define LCD_LAYER0_CSC_COEFF22 … #define LCD_LAYERn_CSC_COEFF22(N) … #define LCD_LAYER0_CSC_COEFF23 … #define LCD_LAYERn_CSC_COEFF23(N) … #define LCD_LAYER0_CSC_COEFF31 … #define LCD_LAYERn_CSC_COEFF31(N) … #define LCD_LAYER0_CSC_COEFF32 … #define LCD_LAYERn_CSC_COEFF32(N) … #define LCD_LAYER0_CSC_COEFF33 … #define LCD_LAYERn_CSC_COEFF33(N) … #define LCD_LAYER0_CSC_OFF1 … #define LCD_LAYERn_CSC_OFF1(N) … #define LCD_LAYER0_CSC_OFF2 … #define LCD_LAYERn_CSC_OFF2(N) … #define LCD_LAYER0_CSC_OFF3 … #define LCD_LAYERn_CSC_OFF3(N) … /* LCD controller Layer DMA config register */ #define LCD_LAYER0_DMA_CFG … #define LCD_LAYERn_DMA_CFG(N) … #define LCD_DMA_LAYER_ENABLE … #define LCD_DMA_LAYER_STATUS … #define LCD_DMA_LAYER_AUTO_UPDATE … #define LCD_DMA_LAYER_CONT_UPDATE … #define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE … #define LCD_DMA_LAYER_FIFO_ADR_MODE … #define LCD_DMA_LAYER_AXI_BURST_1 … #define LCD_DMA_LAYER_AXI_BURST_2 … #define LCD_DMA_LAYER_AXI_BURST_3 … #define LCD_DMA_LAYER_AXI_BURST_4 … #define LCD_DMA_LAYER_AXI_BURST_5 … #define LCD_DMA_LAYER_AXI_BURST_6 … #define LCD_DMA_LAYER_AXI_BURST_7 … #define LCD_DMA_LAYER_AXI_BURST_8 … #define LCD_DMA_LAYER_AXI_BURST_9 … #define LCD_DMA_LAYER_AXI_BURST_10 … #define LCD_DMA_LAYER_AXI_BURST_11 … #define LCD_DMA_LAYER_AXI_BURST_12 … #define LCD_DMA_LAYER_AXI_BURST_13 … #define LCD_DMA_LAYER_AXI_BURST_14 … #define LCD_DMA_LAYER_AXI_BURST_15 … #define LCD_DMA_LAYER_AXI_BURST_16 … #define LCD_DMA_LAYER_VSTRIDE_EN … #define LCD_LAYER0_DMA_START_ADR … #define LCD_LAYERn_DMA_START_ADDR(N) … #define LCD_LAYER0_DMA_START_SHADOW … #define LCD_LAYERn_DMA_START_SHADOW(N) … #define LCD_LAYER0_DMA_LEN … #define LCD_LAYERn_DMA_LEN(N) … #define LCD_LAYER0_DMA_LEN_SHADOW … #define LCD_LAYERn_DMA_LEN_SHADOW(N) … #define LCD_LAYER0_DMA_STATUS … #define LCD_LAYERn_DMA_STATUS(N) … #define LCD_LAYER0_DMA_LINE_WIDTH … #define LCD_LAYERn_DMA_LINE_WIDTH(N) … #define LCD_LAYER0_DMA_LINE_VSTRIDE … #define LCD_LAYERn_DMA_LINE_VSTRIDE(N) … #define LCD_LAYER0_DMA_FIFO_STATUS … #define LCD_LAYERn_DMA_FIFO_STATUS(N) … #define LCD_LAYER0_CFG2 … #define LCD_LAYERn_CFG2(N) … #define LCD_LAYER0_DMA_START_CB_ADR … #define LCD_LAYERn_DMA_START_CB_ADR(N) … #define LCD_LAYER0_DMA_START_CB_SHADOW … #define LCD_LAYERn_DMA_START_CB_SHADOW(N) … #define LCD_LAYER0_DMA_CB_LINE_WIDTH … #define LCD_LAYERn_DMA_CB_LINE_WIDTH(N) … #define LCD_LAYER0_DMA_CB_LINE_VSTRIDE … #define LCD_LAYERn_DMA_CB_LINE_VSTRIDE(N) … #define LCD_LAYER0_DMA_START_CR_ADR … #define LCD_LAYERn_DMA_START_CR_ADR(N) … #define LCD_LAYER0_DMA_START_CR_SHADOW … #define LCD_LAYERn_DMA_START_CR_SHADOW(N) … #define LCD_LAYER0_DMA_CR_LINE_WIDTH … #define LCD_LAYERn_DMA_CR_LINE_WIDTH(N) … #define LCD_LAYER0_DMA_CR_LINE_VSTRIDE … #define LCD_LAYERn_DMA_CR_LINE_VSTRIDE(N) … #define LCD_LAYER1_DMA_START_CB_ADR … #define LCD_LAYER1_DMA_START_CB_SHADOW … #define LCD_LAYER1_DMA_CB_LINE_WIDTH … #define LCD_LAYER1_DMA_CB_LINE_VSTRIDE … #define LCD_LAYER1_DMA_START_CR_ADR … #define LCD_LAYER1_DMA_START_CR_SHADOW … #define LCD_LAYER1_DMA_CR_LINE_WIDTH … #define LCD_LAYER1_DMA_CR_LINE_VSTRIDE … /**************************************************************************** * LCD controller output format register defines ***************************************************************************/ #define LCD_OUT_FORMAT_CFG … #define LCD_OUTF_FORMAT_RGB121212 … #define LCD_OUTF_FORMAT_RGB101010 … #define LCD_OUTF_FORMAT_RGB888 … #define LCD_OUTF_FORMAT_RGB666 … #define LCD_OUTF_FORMAT_RGB565 … #define LCD_OUTF_FORMAT_RGB444 … #define LCD_OUTF_FORMAT_MRGB121212 … #define LCD_OUTF_FORMAT_MRGB101010 … #define LCD_OUTF_FORMAT_MRGB888 … #define LCD_OUTF_FORMAT_MRGB666 … #define LCD_OUTF_FORMAT_MRGB565 … #define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY … #define LCD_OUTF_FORMAT_YCBCR420_8B_DCI … #define LCD_OUTF_FORMAT_YCBCR420_8B … #define LCD_OUTF_FORMAT_YCBCR420_10B … #define LCD_OUTF_FORMAT_YCBCR420_12B … #define LCD_OUTF_FORMAT_YCBCR422_8B … #define LCD_OUTF_FORMAT_YCBCR422_10B … #define LCD_OUTF_FORMAT_YCBCR444 … #define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY … #define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI … #define LCD_OUTF_FORMAT_MYCBCR420_8B … #define LCD_OUTF_FORMAT_MYCBCR420_10B … #define LCD_OUTF_FORMAT_MYCBCR420_12B … #define LCD_OUTF_FORMAT_MYCBCR422_8B … #define LCD_OUTF_FORMAT_MYCBCR422_10B … #define LCD_OUTF_FORMAT_MYCBCR444 … #define LCD_OUTF_BGR_ORDER … #define LCD_OUTF_Y_ORDER … #define LCD_OUTF_CRCB_ORDER … #define LCD_OUTF_SYNC_MODE … #define LCD_OUTF_RGB_CONV_MODE … #define LCD_OUTF_MIPI_RGB_MODE … #define LCD_HSYNC_WIDTH … #define LCD_H_BACKPORCH … #define LCD_H_ACTIVEWIDTH … #define LCD_H_FRONTPORCH … #define LCD_VSYNC_WIDTH … #define LCD_V_BACKPORCH … #define LCD_V_ACTIVEHEIGHT … #define LCD_V_FRONTPORCH … #define LCD_VSYNC_START … #define LCD_VSYNC_END … #define LCD_V_BACKPORCH_EVEN … #define LCD_VSYNC_WIDTH_EVEN … #define LCD_V_ACTIVEHEIGHT_EVEN … #define LCD_V_FRONTPORCH_EVEN … #define LCD_VSYNC_START_EVEN … #define LCD_VSYNC_END_EVEN … #define LCD_TIMING_GEN_TRIG … #define LCD_PWM0_CTRL … #define LCD_PWM0_RPT_LEADIN … #define LCD_PWM0_HIGH_LOW … #define LCD_PWM1_CTRL … #define LCD_PWM1_RPT_LEADIN … #define LCD_PWM1_HIGH_LOW … #define LCD_PWM2_CTRL … #define LCD_PWM2_RPT_LEADIN … #define LCD_PWM2_HIGH_LOW … #define LCD_VIDEO0_DMA0_BYTES … #define LCD_VIDEO0_DMA0_STATE … #define LCD_DMA_STATE_ACTIVE … #define LCD_VIDEO0_DMA1_BYTES … #define LCD_VIDEO0_DMA1_STATE … #define LCD_VIDEO0_DMA2_BYTES … #define LCD_VIDEO0_DMA2_STATE … #define LCD_VIDEO1_DMA0_BYTES … #define LCD_VIDEO1_DMA0_STATE … #define LCD_VIDEO1_DMA1_BYTES … #define LCD_VIDEO1_DMA1_STATE … #define LCD_VIDEO1_DMA2_BYTES … #define LCD_VIDEO1_DMA2_STATE … #define LCD_GRAPHIC0_DMA_BYTES … #define LCD_GRAPHIC0_DMA_STATE … #define LCD_GRAPHIC1_DMA_BYTES … #define LCD_GRAPHIC1_DMA_STATE … /*************************************************************************** * MIPI controller control register defines *************************************************************************/ #define MIPI0_HS_BASE_ADDR … #define HS_OFFSET(M) … #define MIPI_TX_HS_CTRL … #define MIPI_TXm_HS_CTRL(M) … #define HS_CTRL_EN … /* 1:CSI 0:DSI */ #define HS_CTRL_CSIDSIN … /* 1:LCD, 0:DMA */ #define TX_SOURCE … #define ACTIVE_LANES(n) … #define LCD_VC(ch) … #define DSI_EOTP_EN … #define DSI_CMD_HFP_EN … #define CRC_EN … #define HSEXIT_CNT(n) … #define HSCLKIDLE_CNT … #define MIPI_TX_HS_SYNC_CFG … #define MIPI_TXm_HS_SYNC_CFG(M) … #define LINE_SYNC_PKT_ENABLE … #define FRAME_COUNTER_ACTIVE … #define LINE_COUNTER_ACTIVE … #define DSI_V_BLANKING … #define DSI_HSA_BLANKING … #define DSI_HBP_BLANKING … #define DSI_HFP_BLANKING … #define DSI_SYNC_PULSE_EVENTN … #define DSI_LPM_FIRST_VSA_LINE … #define DSI_LPM_LAST_VFP_LINE … #define WAIT_ALL_SECT … #define WAIT_TRIG_POS … #define ALWAYS_USE_HACT(f) … #define FRAME_GEN_EN(f) … #define HACT_WAIT_STOP(f) … #define MIPI_TX0_HS_FG0_SECT0_PH … #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) … #define MIPI_TX_SECT_WC_MASK … #define MIPI_TX_SECT_VC_MASK … #define MIPI_TX_SECT_VC_SHIFT … #define MIPI_TX_SECT_DT_MASK … #define MIPI_TX_SECT_DT_SHIFT … #define MIPI_TX_SECT_DM_MASK … #define MIPI_TX_SECT_DM_SHIFT … #define MIPI_TX_SECT_DMA_PACKED … #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 … #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 … #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) … #define MIPI_TX_HS_FG0_SECT0_LINE_CFG … #define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) … #define MIPI_TX_HS_FG0_NUM_LINES … #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) … #define MIPI_TX_HS_VSYNC_WIDTHS0 … #define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) … #define MIPI_TX_HS_V_BACKPORCHES0 … #define MIPI_TXm_HS_V_BACKPORCHESn(M, N) … #define MIPI_TX_HS_V_FRONTPORCHES0 … #define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) … #define MIPI_TX_HS_V_ACTIVE0 … #define MIPI_TXm_HS_V_ACTIVEn(M, N) … #define MIPI_TX_HS_HSYNC_WIDTH0 … #define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) … #define MIPI_TX_HS_H_BACKPORCH0 … #define MIPI_TXm_HS_H_BACKPORCHn(M, N) … #define MIPI_TX_HS_H_FRONTPORCH0 … #define MIPI_TXm_HS_H_FRONTPORCHn(M, N) … #define MIPI_TX_HS_H_ACTIVE0 … #define MIPI_TXm_HS_H_ACTIVEn(M, N) … #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 … #define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) … #define MIPI_TX_HS_LLP_H_BACKPORCH0 … #define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) … #define MIPI_TX_HS_LLP_H_FRONTPORCH0 … #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) … #define MIPI_TX_HS_MC_FIFO_CTRL_EN … #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) … #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 … #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 … #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) … #define SET_MC_FIFO_CHAN_ALLOC(dev, ctrl, vc, sz) … #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 … #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 … #define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) … #define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) … #define MIPI_TX_HS_DMA_CFG … #define MIPI_TX_HS_DMA_START_ADR_CHAN0 … #define MIPI_TX_HS_DMA_LEN_CHAN0 … /* MIPI IRQ */ #define MIPI_CTRL_IRQ_STATUS0 … #define MIPI_DPHY_ERR_IRQ … #define MIPI_DPHY_ERR_MASK … #define MIPI_HS_IRQ … /* bits 13-22 */ #define MIPI_HS_IRQ_MASK … #define MIPI_LP_EVENT_IRQ … #define MIPI_GET_IRQ_STAT0(dev) … #define MIPI_CTRL_IRQ_STATUS1 … #define MIPI_HS_RX_EVENT_IRQ … #define MIPI_GET_IRQ_STAT1(dev) … #define MIPI_CTRL_IRQ_ENABLE0 … #define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) … #define MIPI_GET_IRQ_ENABLED0(dev) … #define MIPI_CTRL_IRQ_ENABLE1 … #define MIPI_GET_IRQ_ENABLED1(dev) … #define MIPI_CTRL_IRQ_CLEAR0 … #define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) … #define MIPI_CTRL_IRQ_CLEAR1 … #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) … #define MIPI_CTRL_DIG_LOOPBACK … #define MIPI_TX_HS_IRQ_STATUS … #define MIPI_TX_HS_IRQ_STATUSm(M) … #define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) … #define MIPI_TX_HS_IRQ_LINE_COMPARE … #define MIPI_TX_HS_IRQ_FRAME_DONE_0 … #define MIPI_TX_HS_IRQ_FRAME_DONE_1 … #define MIPI_TX_HS_IRQ_FRAME_DONE_2 … #define MIPI_TX_HS_IRQ_FRAME_DONE_3 … #define MIPI_TX_HS_IRQ_DMA_DONE_0 … #define MIPI_TX_HS_IRQ_DMA_IDLE_0 … #define MIPI_TX_HS_IRQ_DMA_DONE_1 … #define MIPI_TX_HS_IRQ_DMA_IDLE_1 … #define MIPI_TX_HS_IRQ_DMA_DONE_2 … #define MIPI_TX_HS_IRQ_DMA_IDLE_2 … #define MIPI_TX_HS_IRQ_DMA_DONE_3 … #define MIPI_TX_HS_IRQ_DMA_IDLE_3 … #define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW … #define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW … #define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY … #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL … #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR … #define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR … #define MIPI_TX_HS_IRQ_FRAME_DONE … #define MIPI_TX_HS_IRQ_DMA_DONE … #define MIPI_TX_HS_IRQ_DMA_IDLE … #define MIPI_TX_HS_IRQ_ERROR … #define MIPI_TX_HS_IRQ_ALL … #define MIPI_TX_HS_IRQ_ENABLE … #define GET_HS_IRQ_ENABLE(dev, M) … #define MIPI_TX_HS_IRQ_CLEAR … /* MIPI Test Pattern Generation */ #define MIPI_TX_HS_TEST_PAT_CTRL … #define MIPI_TXm_HS_TEST_PAT_CTRL(M) … #define TP_EN_VCm(M) … #define TP_SEL_VCm(M, N) … #define TP_STRIPE_WIDTH(M) … #define MIPI_TX_HS_TEST_PAT_COLOR0 … #define MIPI_TXm_HS_TEST_PAT_COLOR0(M) … #define MIPI_TX_HS_TEST_PAT_COLOR1 … #define MIPI_TXm_HS_TEST_PAT_COLOR1(M) … /* D-PHY regs */ #define DPHY_ENABLE … #define DPHY_INIT_CTRL0 … #define SHUTDOWNZ … #define RESETZ … #define DPHY_INIT_CTRL1 … #define PLL_CLKSEL_0 … #define PLL_SHADOW_CTRL … #define DPHY_INIT_CTRL2 … #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) … #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) … #define DPHY_INIT_CTRL2 … #define DPHY_PLL_OBS0 … #define DPHY_PLL_OBS1 … #define DPHY_PLL_OBS2 … #define DPHY_FREQ_CTRL0_3 … #define DPHY_FREQ_CTRL4_7 … #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) … #define DPHY_FORCE_CTRL0 … #define DPHY_FORCE_CTRL1 … #define MIPI_DPHY_STAT0_3 … #define MIPI_DPHY_STAT4_7 … #define GET_STOPSTATE_DATA(dev, dphy) … #define MIPI_DPHY_ERR_STAT6_7 … #define DPHY_TEST_CTRL0 … #define SET_DPHY_TEST_CTRL0(dev, dphy) … #define CLR_DPHY_TEST_CTRL0(dev, dphy) … #define DPHY_TEST_CTRL1 … #define SET_DPHY_TEST_CTRL1_CLK(dev, dphy) … #define CLR_DPHY_TEST_CTRL1_CLK(dev, dphy) … #define SET_DPHY_TEST_CTRL1_EN(dev, dphy) … #define CLR_DPHY_TEST_CTRL1_EN(dev, dphy) … #define DPHY_TEST_DIN0_3 … #define SET_TEST_DIN0_3(dev, dphy, val) … #define DPHY_TEST_DOUT0_3 … #define GET_TEST_DOUT0_3(dev, dphy) … #define DPHY_TEST_DOUT4_7 … #define GET_TEST_DOUT4_7(dev, dphy) … #define DPHY_TEST_DOUT8_9 … #define DPHY_TEST_DIN4_7 … #define DPHY_TEST_DIN8_9 … #define DPHY_PLL_LOCK … #define GET_PLL_LOCK(dev, dphy) … #define DPHY_CFG_CLK_EN … #define MSS_MIPI_CIF_CFG … #define MSS_LCD_MIPI_CFG … #define MSS_CAM_CLK_CTRL … #define MSS_LOOPBACK_CFG … #define LCD … #define MIPI_COMMON … #define MIPI_TX0 … #define MSS_CAM_RSTN_CTRL … #define MSS_CAM_RSTN_SET … #define MSS_CAM_RSTN_CLR … #define MSSCPU_CPR_CLK_EN … #define MSSCPU_CPR_RST_EN … #define BIT_MASK_16 … /* icam lcd qos */ #define LCD_QOS_PRIORITY … #define LCD_QOS_MODE … #define LCD_QOS_BW … #endif /* __KMB_REGS_H__ */
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