linux/drivers/gpu/drm/kmb/kmb_dsi.h

/* SPDX-License-Identifier: GPL-2.0-only
 *
 * Copyright © 2019-2020 Intel Corporation
 */

#ifndef __KMB_DSI_H__
#define __KMB_DSI_H__

#include <drm/drm_encoder.h>
#include <drm/drm_mipi_dsi.h>

/* MIPI TX CFG */
#define MIPI_TX_LANE_DATA_RATE_MBPS …
#define MIPI_TX_REF_CLK_KHZ …
#define MIPI_TX_CFG_CLK_KHZ …
#define MIPI_TX_BPP …

/* DPHY Tx test codes*/
#define TEST_CODE_FSM_CONTROL …
#define TEST_CODE_MULTIPLE_PHY_CTRL …
#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL …
#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL …
#define TEST_CODE_PLL_VCO_CTRL …
#define TEST_CODE_PLL_GMP_CTRL …
#define TEST_CODE_PLL_PHASE_ERR_CTRL …
#define TEST_CODE_PLL_LOCK_FILTER …
#define TEST_CODE_PLL_UNLOCK_FILTER …
#define TEST_CODE_PLL_INPUT_DIVIDER …
#define TEST_CODE_PLL_FEEDBACK_DIVIDER …
#define PLL_FEEDBACK_DIVIDER_HIGH …
#define TEST_CODE_PLL_OUTPUT_CLK_SEL …
#define PLL_N_OVR_EN …
#define PLL_M_OVR_EN …
#define TEST_CODE_VOD_LEVEL …
#define TEST_CODE_PLL_CHARGE_PUMP_BIAS …
#define TEST_CODE_PLL_LOCK_DETECTOR …
#define TEST_CODE_HS_FREQ_RANGE_CFG …
#define TEST_CODE_PLL_ANALOG_PROG …
#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL …
#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL …
#define TEST_CODE_SLEW_RATE_DDL_CYCLES …

/* DPHY params */
#define PLL_N_MIN …
#define PLL_N_MAX …
#define PLL_M_MIN …
#define PLL_M_MAX …
#define PLL_FVCO_MAX …

#define TIMEOUT …

#define MIPI_TX_FRAME_GEN …
#define MIPI_TX_FRAME_GEN_SECTIONS …
#define MIPI_CTRL_VIRTUAL_CHANNELS …
#define MIPI_D_LANES_PER_DPHY …
#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC …
#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC …
/* 2 Data Lanes per D-PHY */
#define MIPI_DPHY_D_LANES …
#define MIPI_DPHY_DEFAULT_BIT_RATES …

#define KMB_MIPI_DEFAULT_CLK …
#define KMB_MIPI_DEFAULT_CFG_CLK …

#define to_kmb_dsi(x) …

struct kmb_dsi { … };

/* DPHY Tx test codes */

enum mipi_ctrl_num { … };

enum mipi_dphy_num { … };

enum mipi_dir { … };

enum mipi_ctrl_type { … };

enum mipi_data_if { … };

enum mipi_data_mode { … };

enum mipi_dsi_video_mode { … };

enum mipi_dsi_blanking_mode { … };

enum mipi_dsi_eotp { … };

enum mipi_dsi_data_type { … };

enum mipi_tx_hs_tp_sel { … };

enum dphy_mode { … };

enum dphy_tx_fsm { … };

struct mipi_data_type_params { … };

struct mipi_tx_dsi_cfg { … };

struct mipi_tx_frame_section_cfg { … };

struct mipi_tx_frame_timing_cfg { … };

struct mipi_tx_frame_sect_phcfg { … };

struct mipi_tx_frame_cfg { … };

struct mipi_tx_ctrl_cfg { … };

/* configuration structure for MIPI control */
struct mipi_ctrl_cfg { … };

static inline void kmb_write_mipi(struct kmb_dsi *kmb_dsi,
				  unsigned int reg, u32 value)
{ … }

static inline u32 kmb_read_mipi(struct kmb_dsi *kmb_dsi, unsigned int reg)
{ … }

static inline void kmb_write_bits_mipi(struct kmb_dsi *kmb_dsi,
				       unsigned int reg, u32 offset,
				       u32 num_bits, u32 value)
{ … }

static inline void kmb_set_bit_mipi(struct kmb_dsi *kmb_dsi,
				    unsigned int reg, u32 offset)
{ … }

static inline void kmb_clr_bit_mipi(struct kmb_dsi *kmb_dsi,
				    unsigned int reg, u32 offset)
{ … }

int kmb_dsi_host_bridge_init(struct device *dev);
struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev);
void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi);
int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
		     int sys_clk_mhz, struct drm_atomic_state *old_state);
int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi);
int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi);
int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi);
#endif /* __KMB_DSI_H__ */