/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLASS_H__ #define __NVIF_CLASS_H__ /* these class numbers are made up by us, and not nvidia-assigned */ #define NVIF_CLASS_CLIENT … #define NVIF_CLASS_CONTROL … #define NVIF_CLASS_SW_NV04 … #define NVIF_CLASS_SW_NV10 … #define NVIF_CLASS_SW_NV50 … #define NVIF_CLASS_SW_GF100 … #define NVIF_CLASS_MMU … #define NVIF_CLASS_MMU_NV04 … #define NVIF_CLASS_MMU_NV50 … #define NVIF_CLASS_MMU_GF100 … #define NVIF_CLASS_MEM … #define NVIF_CLASS_MEM_NV04 … #define NVIF_CLASS_MEM_NV50 … #define NVIF_CLASS_MEM_GF100 … #define NVIF_CLASS_VMM … #define NVIF_CLASS_VMM_NV04 … #define NVIF_CLASS_VMM_NV50 … #define NVIF_CLASS_VMM_GF100 … #define NVIF_CLASS_VMM_GM200 … #define NVIF_CLASS_VMM_GP100 … #define NVIF_CLASS_EVENT … #define NVIF_CLASS_DISP … #define NVIF_CLASS_CONN … #define NVIF_CLASS_OUTP … #define NVIF_CLASS_HEAD … #define NVIF_CLASS_DISP_CHAN … #define NVIF_CLASS_CHAN … #define NVIF_CLASS_CGRP … /* the below match nvidia-assigned (either in hw, or sw) class numbers */ #define NV_NULL_CLASS … #define NV_DEVICE … #define NV_DMA_FROM_MEMORY … #define NV_DMA_TO_MEMORY … #define NV_DMA_IN_MEMORY … #define NV50_TWOD … #define FERMI_TWOD_A … #define NV50_MEMORY_TO_MEMORY_FORMAT … #define FERMI_MEMORY_TO_MEMORY_FORMAT_A … #define KEPLER_INLINE_TO_MEMORY_A … #define KEPLER_INLINE_TO_MEMORY_B … #define NV04_DISP … #define VOLTA_USERMODE_A … #define TURING_USERMODE_A … #define AMPERE_USERMODE_A … #define MAXWELL_FAULT_BUFFER_A … #define VOLTA_FAULT_BUFFER_A … #define NV03_CHANNEL_DMA … #define NV10_CHANNEL_DMA … #define NV17_CHANNEL_DMA … #define NV40_CHANNEL_DMA … #define KEPLER_CHANNEL_GROUP_A … #define NV50_CHANNEL_GPFIFO … #define G82_CHANNEL_GPFIFO … #define FERMI_CHANNEL_GPFIFO … #define KEPLER_CHANNEL_GPFIFO_A … #define KEPLER_CHANNEL_GPFIFO_B … #define MAXWELL_CHANNEL_GPFIFO_A … #define PASCAL_CHANNEL_GPFIFO_A … #define VOLTA_CHANNEL_GPFIFO_A … #define TURING_CHANNEL_GPFIFO_A … #define AMPERE_CHANNEL_GPFIFO_A … #define AMPERE_CHANNEL_GPFIFO_B … #define NV50_DISP … #define G82_DISP … #define GT200_DISP … #define GT214_DISP … #define GT206_DISP … #define GF110_DISP … #define GK104_DISP … #define GK110_DISP … #define GM107_DISP … #define GM200_DISP … #define GP100_DISP … #define GP102_DISP … #define GV100_DISP … #define TU102_DISP … #define GA102_DISP … #define AD102_DISP … #define GV100_DISP_CAPS … #define NV31_MPEG … #define G82_MPEG … #define NV74_VP2 … #define NV50_DISP_CURSOR … #define G82_DISP_CURSOR … #define GT214_DISP_CURSOR … #define GF110_DISP_CURSOR … #define GK104_DISP_CURSOR … #define GV100_DISP_CURSOR … #define TU102_DISP_CURSOR … #define GA102_DISP_CURSOR … #define NV50_DISP_OVERLAY … #define G82_DISP_OVERLAY … #define GT214_DISP_OVERLAY … #define GF110_DISP_OVERLAY … #define GK104_DISP_OVERLAY … #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA … #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA … #define GA102_DISP_WINDOW_IMM_CHANNEL_DMA … #define NV50_DISP_BASE_CHANNEL_DMA … #define G82_DISP_BASE_CHANNEL_DMA … #define GT200_DISP_BASE_CHANNEL_DMA … #define GT214_DISP_BASE_CHANNEL_DMA … #define GF110_DISP_BASE_CHANNEL_DMA … #define GK104_DISP_BASE_CHANNEL_DMA … #define GK110_DISP_BASE_CHANNEL_DMA … #define NV50_DISP_CORE_CHANNEL_DMA … #define G82_DISP_CORE_CHANNEL_DMA … #define GT200_DISP_CORE_CHANNEL_DMA … #define GT214_DISP_CORE_CHANNEL_DMA … #define GT206_DISP_CORE_CHANNEL_DMA … #define GF110_DISP_CORE_CHANNEL_DMA … #define GK104_DISP_CORE_CHANNEL_DMA … #define GK110_DISP_CORE_CHANNEL_DMA … #define GM107_DISP_CORE_CHANNEL_DMA … #define GM200_DISP_CORE_CHANNEL_DMA … #define GP100_DISP_CORE_CHANNEL_DMA … #define GP102_DISP_CORE_CHANNEL_DMA … #define GV100_DISP_CORE_CHANNEL_DMA … #define TU102_DISP_CORE_CHANNEL_DMA … #define GA102_DISP_CORE_CHANNEL_DMA … #define AD102_DISP_CORE_CHANNEL_DMA … #define NV50_DISP_OVERLAY_CHANNEL_DMA … #define G82_DISP_OVERLAY_CHANNEL_DMA … #define GT200_DISP_OVERLAY_CHANNEL_DMA … #define GT214_DISP_OVERLAY_CHANNEL_DMA … #define GF110_DISP_OVERLAY_CONTROL_DMA … #define GK104_DISP_OVERLAY_CONTROL_DMA … #define GV100_DISP_WINDOW_CHANNEL_DMA … #define TU102_DISP_WINDOW_CHANNEL_DMA … #define GA102_DISP_WINDOW_CHANNEL_DMA … #define NV50_TESLA … #define G82_TESLA … #define GT200_TESLA … #define GT214_TESLA … #define GT21A_TESLA … #define FERMI_A … #define FERMI_B … #define FERMI_C … #define KEPLER_A … #define KEPLER_B … #define KEPLER_C … #define MAXWELL_A … #define MAXWELL_B … #define PASCAL_A … #define PASCAL_B … #define VOLTA_A … #define TURING_A … #define AMPERE_B … #define ADA_A … #define NV74_BSP … #define NVC4B0_VIDEO_DECODER … #define NVC6B0_VIDEO_DECODER … #define NVC7B0_VIDEO_DECODER … #define NVC9B0_VIDEO_DECODER … #define GT212_MSVLD … #define IGT21A_MSVLD … #define G98_MSVLD … #define GF100_MSVLD … #define GK104_MSVLD … #define GT212_MSPDEC … #define G98_MSPDEC … #define GF100_MSPDEC … #define GK104_MSPDEC … #define GT212_MSPPP … #define G98_MSPPP … #define GF100_MSPPP … #define G98_SEC … #define GT212_DMA … #define FERMI_DMA … #define KEPLER_DMA_COPY_A … #define MAXWELL_DMA_COPY_A … #define PASCAL_DMA_COPY_A … #define PASCAL_DMA_COPY_B … #define VOLTA_DMA_COPY_A … #define TURING_DMA_COPY_A … #define AMPERE_DMA_COPY_A … #define AMPERE_DMA_COPY_B … #define NVC4B7_VIDEO_ENCODER … #define NVC7B7_VIDEO_ENCODER … #define NVC9B7_VIDEO_ENCODER … #define FERMI_DECOMPRESS … #define NV50_COMPUTE … #define GT214_COMPUTE … #define FERMI_COMPUTE_A … #define FERMI_COMPUTE_B … #define KEPLER_COMPUTE_A … #define KEPLER_COMPUTE_B … #define MAXWELL_COMPUTE_A … #define MAXWELL_COMPUTE_B … #define PASCAL_COMPUTE_A … #define PASCAL_COMPUTE_B … #define VOLTA_COMPUTE_A … #define TURING_COMPUTE_A … #define AMPERE_COMPUTE_B … #define ADA_COMPUTE_A … #define NV74_CIPHER … #define NVC4D1_VIDEO_NVJPG … #define NVC9D1_VIDEO_NVJPG … #define NVC6FA_VIDEO_OFA … #define NVC7FA_VIDEO_OFA … #define NVC9FA_VIDEO_OFA … #endif
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