linux/arch/sh/include/cpu-sh4/cpu/sh7724.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH7724_H__
#define __ASM_SH7724_H__

/* Boot Mode Pins:
 *
 * MD0: CPG - Clock Mode 0->7
 * MD1: CPG - Clock Mode 0->7
 * MD2: CPG - Clock Mode 0->7
 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
 * MD8: Test Mode
 * BOOT: FBR - Boot Mode (L: MMCIF, H: Area0)
 */

/* Pin Function Controller:
 * GPIO_FN_xx - GPIO used to select pin function
 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
 */
enum { … };

enum { … };

enum { … };

extern struct clk sh7724_fsimcka_clk;
extern struct clk sh7724_fsimckb_clk;
extern struct clk sh7724_dv_clki;

#endif /* __ASM_SH7724_H__ */