// SPDX-License-Identifier: GPL-2.0 /* * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC * * Copyright (C) 2017 Jacopo Mondi */ /* * This pin controller/gpio combined driver supports Renesas devices of RZ/A1 * family. * This includes SoCs which are sub- or super- sets of this particular line, * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020). */ #include <linux/bitops.h> #include <linux/err.h> #include <linux/gpio/driver.h> #include <linux/init.h> #include <linux/ioport.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/slab.h> #include "../core.h" #include "../devicetree.h" #include "../pinconf.h" #include "../pinmux.h" #define DRIVER_NAME … #define RZA1_P_REG … #define RZA1_PPR_REG … #define RZA1_PM_REG … #define RZA1_PMC_REG … #define RZA1_PFC_REG … #define RZA1_PFCE_REG … #define RZA1_PFCEA_REG … #define RZA1_PIBC_REG … #define RZA1_PBDC_REG … #define RZA1_PIPC_REG … #define RZA1_ADDR(mem, reg, port) … #define RZA1_NPORTS … #define RZA1_PINS_PER_PORT … #define RZA1_NPINS … #define RZA1_PIN_ID_TO_PORT(id) … #define RZA1_PIN_ID_TO_PIN(id) … /* * Use 16 lower bits [15:0] for pin identifier * Use 16 higher bits [31:16] for pin mux function */ #define MUX_PIN_ID_MASK … #define MUX_FUNC_MASK … #define MUX_FUNC_OFFS … #define MUX_FUNC(pinconf) … #define MUX_FUNC_PFC_MASK … #define MUX_FUNC_PFCE_MASK … #define MUX_FUNC_PFCEA_MASK … /* Pin mux flags */ #define MUX_FLAGS_BIDIR … #define MUX_FLAGS_SWIO_INPUT … #define MUX_FLAGS_SWIO_OUTPUT … /* ---------------------------------------------------------------------------- * RZ/A1 pinmux flags */ /* * rza1_bidir_pin - describe a single pin that needs bidir flag applied. */ struct rza1_bidir_pin { … }; /* * rza1_bidir_entry - describe a list of pins that needs bidir flag applied. * Each struct rza1_bidir_entry describes a port. */ struct rza1_bidir_entry { … }; /* * rza1_swio_pin - describe a single pin that needs swio flag applied. */ struct rza1_swio_pin { … }; /* * rza1_swio_entry - describe a list of pins that needs swio flag applied */ struct rza1_swio_entry { … }; /* * rza1_pinmux_conf - group together bidir and swio pinmux flag tables */ struct rza1_pinmux_conf { … }; /* ---------------------------------------------------------------------------- * RZ/A1H (r7s72100) pinmux flags */ static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = …; static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = …; static const struct rza1_swio_pin rza1h_swio_pins[] = …; static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = …; static const struct rza1_swio_entry rza1h_swio_entries[] = …; /* RZ/A1H (r7s72100x) pinmux flags table */ static const struct rza1_pinmux_conf rza1h_pmx_conf = …; /* ---------------------------------------------------------------------------- * RZ/A1L (r7s72102) pinmux flags */ static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = …; static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = …; static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = …; static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = …; static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = …; static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = …; static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = …; static const struct rza1_swio_pin rza1l_swio_pins[] = …; static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = …; static const struct rza1_swio_entry rza1l_swio_entries[] = …; /* RZ/A1L (r7s72102x) pinmux flags table */ static const struct rza1_pinmux_conf rza1l_pmx_conf = …; /* ---------------------------------------------------------------------------- * RZ/A1 types */ /** * struct rza1_mux_conf - describes a pin multiplexing operation * * @id: the pin identifier from 0 to RZA1_NPINS * @port: the port where pin sits on * @pin: pin id * @mux_func: alternate function id number * @mux_flags: alternate function flags * @value: output value to set the pin to */ struct rza1_mux_conf { … }; /** * struct rza1_port - describes a pin port * * This is mostly useful to lock register writes per-bank and not globally. * * @lock: protect access to HW registers * @id: port number * @base: logical address base * @pins: pins sitting on this port */ struct rza1_port { … }; /** * struct rza1_pinctrl - RZ pincontroller device * * @dev: parent device structure * @mutex: protect [pinctrl|pinmux]_generic functions * @base: logical address base * @nport: number of pin controller ports * @ports: pin controller banks * @pins: pin array for pinctrl core * @desc: pincontroller desc for pinctrl core * @pctl: pinctrl device * @data: device specific data */ struct rza1_pinctrl { … }; /* ---------------------------------------------------------------------------- * RZ/A1 pinmux flags */ static inline bool rza1_pinmux_get_bidir(unsigned int port, unsigned int pin, unsigned int func, const struct rza1_bidir_entry *table) { … } static inline int rza1_pinmux_get_swio(unsigned int port, unsigned int pin, unsigned int func, const struct rza1_swio_entry *table) { … } /* * rza1_pinmux_get_flags() - return pinmux flags associated to a pin */ static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, unsigned int func, struct rza1_pinctrl *rza1_pctl) { … } /* ---------------------------------------------------------------------------- * RZ/A1 SoC operations */ /* * rza1_set_bit() - un-locked set/clear a single bit in pin configuration * registers */ static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg, unsigned int bit, bool set) { … } static inline unsigned int rza1_get_bit(struct rza1_port *port, unsigned int reg, unsigned int bit) { … } /** * rza1_pin_reset() - reset a pin to default initial state * * Reset pin state disabling input buffer and bi-directional control, * and configure it as input port. * Note that pin is now configured with direction as input but with input * buffer disabled. This implies the pin value cannot be read in this state. * * @port: port where pin sits on * @pin: pin offset */ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) { … } /** * rza1_pin_set_direction() - set I/O direction on a pin in port mode * * When running in output port mode keep PBDC enabled to allow reading the * pin value from PPR. * * @port: port where pin sits on * @pin: pin offset * @input: input enable/disable flag */ static inline void rza1_pin_set_direction(struct rza1_port *port, unsigned int pin, bool input) { … } static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, unsigned int value) { … } static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) { … } /** * rza1_pin_mux_single() - configure pin multiplexing on a single pin * * @rza1_pctl: RZ/A1 pin controller device * @mux_conf: pin multiplexing descriptor */ static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, struct rza1_mux_conf *mux_conf) { … } /* ---------------------------------------------------------------------------- * gpio operations */ /** * rza1_gpio_request() - configure pin in port mode * * Configure a pin as gpio (port mode). * After reset, the pin is in input mode with input buffer disabled. * To use the pin as input or output, set_direction shall be called first * * @chip: gpio chip where the gpio sits on * @gpio: gpio offset */ static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) { … } /** * rza1_gpio_free() - reset a pin * * Surprisingly, freeing a gpio is equivalent to requesting it. * Reset pin to port mode, with input buffer disabled. This overwrites all * port direction settings applied with set_direction * * @chip: gpio chip where the gpio sits on * @gpio: gpio offset */ static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio) { … } static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) { … } static int rza1_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) { … } static int rza1_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, int value) { … } /** * rza1_gpio_get() - read a gpio pin value * * Read gpio pin value through PPR register. * Requires bi-directional mode to work when reading the value of a pin * in output mode * * @chip: gpio chip where the gpio sits on * @gpio: gpio offset */ static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio) { … } static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) { … } static const struct gpio_chip rza1_gpiochip_template = …; /* ---------------------------------------------------------------------------- * pinctrl operations */ /** * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its * children sub-nodes * * @np: device tree node to parse */ static int rza1_dt_node_pin_count(struct device_node *np) { … } /** * rza1_parse_pinmux_node() - parse a pin mux sub-node * * @rza1_pctl: RZ/A1 pin controller device * @np: of pmx sub-node * @mux_confs: array of pin mux configurations to fill with parsed info * @grpins: array of pin ids to mux */ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, struct device_node *np, struct rza1_mux_conf *mux_confs, unsigned int *grpins) { … } /** * rza1_dt_node_to_map() - map a pin mux node to a function/group * * Parse and register a pin mux function. * * @pctldev: pin controller device * @np: device tree node to parse * @map: pointer to pin map (output) * @num_maps: number of collected maps (output) */ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps) { … } static void rza1_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned int num_maps) { … } static const struct pinctrl_ops rza1_pinctrl_ops = …; /* ---------------------------------------------------------------------------- * pinmux operations */ /** * rza1_set_mux() - retrieve pins from a group and apply their mux settings * * @pctldev: pin controller device * @selector: function selector * @group: group selector */ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { … } static const struct pinmux_ops rza1_pinmux_ops = …; /* ---------------------------------------------------------------------------- * RZ/A1 pin controller driver operations */ /** * rza1_parse_gpiochip() - parse and register a gpio chip and pin range * * The gpio controller subnode shall provide a "gpio-ranges" list property as * defined by gpio device tree binding documentation. * * @rza1_pctl: RZ/A1 pin controller device * @fwnode: gpio-controller firmware node * @chip: gpio chip to register to gpiolib * @range: pin range to register to pinctrl core */ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, struct fwnode_handle *fwnode, struct gpio_chip *chip, struct pinctrl_gpio_range *range) { … } /** * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges * * @rza1_pctl: RZ/A1 pin controller device */ static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl) { … } /** * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register * them to pinctrl and gpio cores. * * @rza1_pctl: RZ/A1 pin controller device */ static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl) { … } static int rza1_pinctrl_probe(struct platform_device *pdev) { … } static const struct of_device_id rza1_pinctrl_of_match[] = …; static struct platform_driver rza1_pinctrl_driver = …; static int __init rza1_pinctrl_init(void) { … } core_initcall(rza1_pinctrl_init); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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