// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2014-2018 Renesas Electronics Europe Limited * * Phil Edworthy <[email protected]> * Based on a driver originally written by Michel Pollet at Renesas. */ #include <dt-bindings/pinctrl/rzn1-pinctrl.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" /* Field positions and masks in the pinmux registers */ #define RZN1_L1_PIN_DRIVE_STRENGTH … #define RZN1_L1_PIN_DRIVE_STRENGTH_4MA … #define RZN1_L1_PIN_DRIVE_STRENGTH_6MA … #define RZN1_L1_PIN_DRIVE_STRENGTH_8MA … #define RZN1_L1_PIN_DRIVE_STRENGTH_12MA … #define RZN1_L1_PIN_PULL … #define RZN1_L1_PIN_PULL_NONE … #define RZN1_L1_PIN_PULL_UP … #define RZN1_L1_PIN_PULL_DOWN … #define RZN1_L1_FUNCTION … #define RZN1_L1_FUNC_MASK … #define RZN1_L1_FUNCTION_L2 … /* * The hardware manual describes two levels of multiplexing, but it's more * logical to think of the hardware as three levels, with level 3 consisting of * the multiplexing for Ethernet MDIO signals. * * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying * that level 2 functions are used instead. Level 2 has a lot more options, * going from 0 to 61. Level 3 allows selection of MDIO functions which can be * floating, or one of seven internal peripherals. Unfortunately, there are two * level 2 functions that can select MDIO, and two MDIO channels so we have four * sets of level 3 functions. * * For this driver, we've compounded the numbers together, so: * 0 to 9 is level 1 * 10 to 71 is 10 + level 2 number * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function. * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function. * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function. * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function. * Examples: * Function 28 corresponds UART0 * Function 73 corresponds to MDIO0 to GMAC0 * * There are 170 configurable pins (called PL_GPIO in the datasheet). */ /* * Structure detailing the HW registers on the RZ/N1 devices. * Both the Level 1 mux registers and Level 2 mux registers have the same * structure. The only difference is that Level 2 has additional MDIO registers * at the end. */ struct rzn1_pinctrl_regs { … }; /** * struct rzn1_pmx_func - describes rzn1 pinmux functions * @name: the name of this specific function * @groups: corresponding pin groups * @num_groups: the number of groups */ struct rzn1_pmx_func { … }; /** * struct rzn1_pin_group - describes an rzn1 pin group * @name: the name of this specific pin group * @func: the name of the function selected by this group * @npins: the number of pins in this group array, i.e. the number of * elements in .pins so we can iterate over that array * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins() * @pin_ids: array of pin_ids, i.e. the value used to select the mux */ struct rzn1_pin_group { … }; struct rzn1_pinctrl { … }; #define RZN1_PINS_PROP … #define RZN1_PIN(pin) … static const struct pinctrl_pin_desc rzn1_pins[] = …; enum { … }; static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value) { … } static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio, u32 func) { … } /* * Using a composite pin description, set the hardware pinmux registers * with the corresponding values. * Make sure to unlock write protection and reset it afterward. * * NOTE: There is no protection for potential concurrency, it is assumed these * calls are serialized already. */ static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin, u32 pin_config, u8 use_locks) { … } static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name( const struct rzn1_pinctrl *ipctl, const char *name) { … } static int rzn1_get_groups_count(struct pinctrl_dev *pctldev) { … } static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) { … } static int rzn1_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, const unsigned int **pins, unsigned int *npins) { … } /* * This function is called for each pinctl 'Function' node. * Sub-nodes can be used to describe multiple 'Groups' for the 'Function' * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'. * Each 'Group' uses pinmux = <...> to detail the pins and data used to select * the functionality. Each 'Group' has optional pin configurations that apply * to all pins in the 'Group'. */ static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps) { … } static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps) { … } static const struct pinctrl_ops rzn1_pctrl_ops = …; static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) { … } static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev, unsigned int selector) { … } static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, const char * const **groups, unsigned int * const num_groups) { … } static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { … } static const struct pinmux_ops rzn1_pmx_ops = …; static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { … } static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { … } static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int selector, unsigned long *config) { … } static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector, unsigned long *configs, unsigned int num_configs) { … } static const struct pinconf_ops rzn1_pinconf_ops = …; static struct pinctrl_desc rzn1_pinctrl_desc = …; static int rzn1_pinctrl_parse_groups(struct device_node *np, struct rzn1_pin_group *grp, struct rzn1_pinctrl *ipctl) { … } static int rzn1_pinctrl_count_function_groups(struct device_node *np) { … } static int rzn1_pinctrl_parse_functions(struct device_node *np, struct rzn1_pinctrl *ipctl, unsigned int index) { … } static int rzn1_pinctrl_probe_dt(struct platform_device *pdev, struct rzn1_pinctrl *ipctl) { … } static int rzn1_pinctrl_probe(struct platform_device *pdev) { … } static void rzn1_pinctrl_remove(struct platform_device *pdev) { … } static const struct of_device_id rzn1_pinctrl_match[] = …; MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match); static struct platform_driver rzn1_pinctrl_driver = …; static int __init _pinctrl_drv_register(void) { … } subsys_initcall(_pinctrl_drv_register); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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