// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/V2M Pin Control and GPIO driver core * * Based on: * Renesas RZ/G2L Pin Control and GPIO driver core * * Copyright (C) 2022 Renesas Electronics Corporation. */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/io.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/spinlock.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <dt-bindings/pinctrl/rzv2m-pinctrl.h> #include "../core.h" #include "../pinconf.h" #include "../pinmux.h" #define DRV_NAME … /* * Use 16 lower bits [15:0] for pin identifier * Use 16 higher bits [31:16] for pin mux function */ #define MUX_PIN_ID_MASK … #define MUX_FUNC_MASK … #define MUX_FUNC(pinconf) … /* PIN capabilities */ #define PIN_CFG_GRP_1_8V_2 … #define PIN_CFG_GRP_1_8V_3 … #define PIN_CFG_GRP_SWIO_1 … #define PIN_CFG_GRP_SWIO_2 … #define PIN_CFG_GRP_3_3V … #define PIN_CFG_GRP_MASK … #define PIN_CFG_BIAS … #define PIN_CFG_DRV … #define PIN_CFG_SLEW … #define RZV2M_MPXED_PIN_FUNCS … /* * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ #define RZV2M_GPIO_PORT_PACK(n, a, f) … #define RZV2M_GPIO_PORT_GET_PINCNT(x) … #define RZV2M_GPIO_PORT_GET_INDEX(x) … #define RZV2M_GPIO_PORT_GET_CFGS(x) … #define RZV2M_DEDICATED_PORT_IDX … /* * BIT(31) indicates dedicated pin, b is the register bits (b * 16) * and f is the pin configuration capabilities supported. */ #define RZV2M_SINGLE_PIN … #define RZV2M_SINGLE_PIN_PACK(b, f) … #define RZV2M_SINGLE_PIN_GET_PORT(x) … #define RZV2M_SINGLE_PIN_GET_BIT(x) … #define RZV2M_SINGLE_PIN_GET_CFGS(x) … #define RZV2M_PIN_ID_TO_PORT(id) … #define RZV2M_PIN_ID_TO_PIN(id) … #define DO(n) … #define OE(n) … #define IE(n) … #define PFSEL(n) … #define DI(n) … #define PUPD(n) … #define DRV(n) … #define SR(n) … #define DI_MSK(n) … #define EN_MSK(n) … #define PFC_MASK … #define PUPD_MASK … #define DRV_MASK … struct rzv2m_dedicated_configs { … }; struct rzv2m_pinctrl_data { … }; struct rzv2m_pinctrl { … }; static const unsigned int drv_1_8V_group2_uA[] = …; static const unsigned int drv_1_8V_group3_uA[] = …; static const unsigned int drv_SWIO_group2_3_3V_uA[] = …; static const unsigned int drv_3_3V_group_uA[] = …; /* Helper for registers that have a write enable bit in the upper word */ static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value) { … } static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl, u8 port, u8 pin, u8 func) { void __iomem *addr; /* Mask input/output */ rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); /* Select the function and set the write enable bits */ addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr); /* Unmask input/output */ rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); }; static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, unsigned int group_selector) { struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); struct function_desc *func; unsigned int i, *psel_val; struct group_desc *group; const unsigned int *pins; func = pinmux_generic_get_function(pctldev, func_selector); if (!func) return -EINVAL; group = pinctrl_generic_get_group(pctldev, group_selector); if (!group) return -EINVAL; psel_val = func->data; pins = group->grp.pins; for (i = 0; i < group->grp.npins; i++) { dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]); rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]); } return 0; }; static int rzv2m_map_add_config(struct pinctrl_map *map, const char *group_or_pin, enum pinctrl_map_type type, unsigned long *configs, unsigned int num_configs) { … } static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct device_node *parent, struct pinctrl_map **map, unsigned int *num_maps, unsigned int *index) { … } static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned int num_maps) { … } static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps) { … } static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl, u32 cfg, u32 port, u8 bit) { … } static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset, u8 shift, u32 mask, u32 val) { … } static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) { struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; unsigned int arg = 0; u32 port; u32 cfg; u8 bit; u32 val; if (!pin_data) return -EINVAL; if (*pin_data & RZV2M_SINGLE_PIN) { port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data); cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data); } else { cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data); port = RZV2M_PIN_ID_TO_PORT(_pin); bit = RZV2M_PIN_ID_TO_PIN(_pin); if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) return -EINVAL; } switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: { enum pin_config_param bias; if (!(cfg & PIN_CFG_BIAS)) return -EINVAL; /* PUPD uses 2-bits per pin */ bit *= 2; switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { case 0: bias = PIN_CONFIG_BIAS_PULL_DOWN; break; case 2: bias = PIN_CONFIG_BIAS_PULL_UP; break; default: bias = PIN_CONFIG_BIAS_DISABLE; } if (bias != param) return -EINVAL; break; } case PIN_CONFIG_DRIVE_STRENGTH_UA: if (!(cfg & PIN_CFG_DRV)) return -EINVAL; /* DRV uses 2-bits per pin */ bit *= 2; val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; switch (cfg & PIN_CFG_GRP_MASK) { case PIN_CFG_GRP_1_8V_2: arg = drv_1_8V_group2_uA[val]; break; case PIN_CFG_GRP_1_8V_3: arg = drv_1_8V_group3_uA[val]; break; case PIN_CFG_GRP_SWIO_2: arg = drv_SWIO_group2_3_3V_uA[val]; break; case PIN_CFG_GRP_SWIO_1: case PIN_CFG_GRP_3_3V: arg = drv_3_3V_group_uA[val]; break; default: return -EINVAL; } break; case PIN_CONFIG_SLEW_RATE: if (!(cfg & PIN_CFG_SLEW)) return -EINVAL; arg = readl(pctrl->base + SR(port)) & BIT(bit); break; default: return -ENOTSUPP; } *config = pinconf_to_config_packed(param, arg); return 0; }; static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *_configs, unsigned int num_configs) { … } static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *configs, unsigned int num_configs) { const unsigned int *pins; unsigned int i, npins; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs, num_configs); if (ret) return ret; } return 0; }; static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { const unsigned int *pins; unsigned int i, npins, prev_config = 0; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config); if (ret) return ret; /* Check config matches previous pins */ if (i && prev_config != *config) return -EOPNOTSUPP; prev_config = *config; } return 0; }; static const struct pinctrl_ops rzv2m_pinctrl_pctlops = …; static const struct pinmux_ops rzv2m_pinctrl_pmxops = …; static const struct pinconf_ops rzv2m_pinctrl_confops = …; static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset) { … } static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port, u8 bit, bool output) { … } static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static int rzv2m_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { … } static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { … } static int rzv2m_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { … } static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset) { … } static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset) { … } static const char * const rzv2m_gpio_names[] = …; static const u32 rzv2m_gpio_configs[] = …; static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = …; static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl) { … } static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) { … } static int rzv2m_pinctrl_probe(struct platform_device *pdev) { … } static struct rzv2m_pinctrl_data r9a09g011_data = …; static const struct of_device_id rzv2m_pinctrl_of_table[] = …; static struct platform_driver rzv2m_pinctrl_driver = …; static int __init rzv2m_pinctrl_init(void) { … } core_initcall(rzv2m_pinctrl_init); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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