// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/G2L Pin Control and GPIO driver core * * Copyright (C) 2021 Renesas Electronics Corporation. */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/seq_file.h> #include <linux/spinlock.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> #include "../core.h" #include "../pinconf.h" #include "../pinmux.h" #define DRV_NAME … /* * Use 16 lower bits [15:0] for pin identifier * Use 16 higher bits [31:16] for pin mux function */ #define MUX_PIN_ID_MASK … #define MUX_FUNC_MASK … /* PIN capabilities */ #define PIN_CFG_IOLH_A … #define PIN_CFG_IOLH_B … #define PIN_CFG_SR … #define PIN_CFG_IEN … #define PIN_CFG_PUPD … #define PIN_CFG_IO_VMC_SD0 … #define PIN_CFG_IO_VMC_SD1 … #define PIN_CFG_IO_VMC_QSPI … #define PIN_CFG_IO_VMC_ETH0 … #define PIN_CFG_IO_VMC_ETH1 … #define PIN_CFG_NF … #define PIN_CFG_IOLH_C … #define PIN_CFG_SOFT_PS … #define PIN_CFG_OEN … #define PIN_CFG_NOGPIO_INT … #define PIN_CFG_NOD … #define PIN_CFG_SMT … #define PIN_CFG_ELC … #define PIN_CFG_IOLH_RZV2H … #define RZG2L_SINGLE_PIN … #define RZG2L_VARIABLE_CFG … #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) … #define RZG2L_MPXED_PIN_FUNCS … #define RZG3S_MPXED_PIN_FUNCS(group) … #define RZV2H_MPXED_PIN_FUNCS … #define RZG2L_MPXED_ETH_PIN_FUNCS(x) … #define PIN_CFG_PIN_MAP_MASK … #define PIN_CFG_PIN_REG_MASK … #define PIN_CFG_MASK … /* * m indicates the bitmap of supported pins, a is the register index * and f is pin configuration capabilities supported. */ #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) … #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) … /* * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ #define RZG2L_GPIO_PORT_PACK(n, a, f) … #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) … #define RZG2L_SINGLE_PIN_INDEX_MASK … #define RZG2L_SINGLE_PIN_BITS_MASK … /* * p is the register index while referencing to SR/IEN/IOLH/FILxx * registers, b is the register bits (b * 8) and f is the pin * configuration capabilities supported. */ #define RZG2L_SINGLE_PIN_PACK(p, b, f) … #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) … #define VARIABLE_PIN_CFG_PIN_MASK … #define VARIABLE_PIN_CFG_PORT_MASK … #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) … #define P(off) … #define PM(off) … #define PMC(off) … #define PFC(off) … #define PIN(off) … #define IOLH(off) … #define SR(off) … #define IEN(off) … #define PUPD(off) … #define ISEL(off) … #define SD_CH(off, ch) … #define ETH_POC(off, ch) … #define QSPI … #define ETH_MODE … #define PFC_OEN … #define PVDD_2500 … #define PVDD_1800 … #define PVDD_3300 … #define PWPR_B0WI … #define PWPR_PFCWE … #define PWPR_REGWE_A … #define PWPR_REGWE_B … #define PM_MASK … #define PFC_MASK … #define IEN_MASK … #define IOLH_MASK … #define SR_MASK … #define PUPD_MASK … #define PM_INPUT … #define PM_OUTPUT … #define RZG2L_PIN_ID_TO_PORT(id) … #define RZG2L_PIN_ID_TO_PIN(id) … #define RZG2L_TINT_MAX_INTERRUPT … #define RZG2L_TINT_IRQ_START_INDEX … #define RZG2L_PACK_HWIRQ(t, i) … /* Custom pinconf parameters */ #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE … static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = …; #ifdef CONFIG_DEBUG_FS static const struct pin_config_item renesas_rzv2h_conf_items[] = …; #endif /* Read/write 8 bits register */ #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) … /* Read/write 16 bits register */ #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) … /* Read/write 32 bits register */ #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) … /** * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset */ struct rzg2l_register_offsets { … }; /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source * @RZG2L_IOLH_IDX_MAX: maximum index */ enum rzg2l_iolh_index { … }; /* Maximum number of driver strength entries per power source. */ #define RZG2L_IOLH_MAX_DS_ENTRIES … /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values * @iolh_groupb_oi: IOLH group B output impedance specific values * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable */ struct rzg2l_hwcfg { … }; struct rzg2l_dedicated_configs { … }; struct rzg2l_pinctrl; struct rzg2l_pinctrl_data { … }; /** * struct rzg2l_pinctrl_pin_settings - pin data * @power_source: power source * @drive_strength_ua: drive strength (in micro amps) */ struct rzg2l_pinctrl_pin_settings { … }; /** * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) * @p: P registers cache * @pm: PM registers cache * @pmc: PMC registers cache * @pfc: PFC registers cache * @iolh: IOLH registers cache * @ien: IEN registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @eth_mode: ETH_MODE register cache * @qspi: QSPI registers cache */ struct rzg2l_pinctrl_reg_cache { … }; struct rzg2l_pinctrl { … }; static const u16 available_ps[] = …; static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, unsigned int port, u8 pin) { … } static const u64 r9a09g057_variable_pin_cfg[] = …; #ifdef CONFIG_RISCV static const u64 r9a07g043f_variable_pin_cfg[] = { RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO_INT), RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NF | PIN_CFG_NOGPIO_INT), }; #endif static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) { … } static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) { … } static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { unsigned long flags; u32 reg; spin_lock_irqsave(&pctrl->lock, flags); /* Set pin to 'Non-use (Hi-Z input protection)' */ reg = readw(pctrl->base + PM(off)); reg &= ~(PM_MASK << (pin * 2)); writew(reg, pctrl->base + PM(off)); pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); /* Temporarily switch to GPIO mode with PMC register */ reg = readb(pctrl->base + PMC(off)); writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); /* Select Pin function mode with PFC register */ reg = readl(pctrl->base + PFC(off)); reg &= ~(PFC_MASK << (pin * 4)); writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); /* Switch to Peripheral pin function with PMC register */ reg = readb(pctrl->base + PMC(off)); writeb(reg | BIT(pin), pctrl->base + PMC(off)); pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); spin_unlock_irqrestore(&pctrl->lock, flags); }; static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, unsigned int group_selector) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct function_desc *func; unsigned int i, *psel_val; struct group_desc *group; const unsigned int *pins; func = pinmux_generic_get_function(pctldev, func_selector); if (!func) return -EINVAL; group = pinctrl_generic_get_group(pctldev, group_selector); if (!group) return -EINVAL; psel_val = func->data; pins = group->grp.pins; for (i = 0; i < group->grp.npins; i++) { u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0; }; static int rzg2l_map_add_config(struct pinctrl_map *map, const char *group_or_pin, enum pinctrl_map_type type, unsigned long *configs, unsigned int num_configs) { … } static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct device_node *parent, struct pinctrl_map **map, unsigned int *num_maps, unsigned int *index) { … } static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned int num_maps) { … } static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps) { … } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, u64 cfg, u32 port, u8 bit) { … } static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, u8 bit, u32 mask) { … } static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, u8 bit, u32 mask, u32 val) { … } static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) { … } static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) { … } static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) { … } static bool rzg2l_ps_is_supported(u16 ps) { … } static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) { … } static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) { … } static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, enum rzg2l_iolh_index ps_index, u16 ua) { … } static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, enum rzg2l_iolh_index iolh_idx, u16 ds) { … } static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { … } static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { … } static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { … } static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { … } static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { … } static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { … } static int rzg2l_hw_to_bias_param(unsigned int bias) { … } static int rzg2l_bias_param_to_hw(enum pin_config_param param) { … } static int rzv2h_hw_to_bias_param(unsigned int bias) { … } static int rzv2h_bias_param_to_hw(enum pin_config_param param) { … } static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { … } static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { … } static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { … } static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; u32 param = pinconf_to_config_param(*config); u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off; u32 cfg; int ret; u8 bit; if (!pin_data) return -EINVAL; off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit = RZG2L_PIN_ID_TO_PIN(_pin); if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) return -EINVAL; } switch (param) { case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) return -EINVAL; arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); if (!arg) return -EINVAL; break; case PIN_CONFIG_OUTPUT_ENABLE: if (!(cfg & PIN_CFG_OEN)) return -EINVAL; if (!pctrl->data->oen_read) return -EOPNOTSUPP; arg = pctrl->data->oen_read(pctrl, _pin); if (!arg) return -EINVAL; break; case PIN_CONFIG_POWER_SOURCE: ret = rzg2l_get_power_source(pctrl, _pin, cfg); if (ret < 0) return ret; arg = ret; break; case PIN_CONFIG_SLEW_RATE: if (!(cfg & PIN_CFG_SR)) return -EINVAL; arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); break; case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: if (!(cfg & PIN_CFG_PUPD)) return -EINVAL; arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); ret = pctrl->data->hw_to_bias_param(arg); if (ret < 0) return ret; if (ret != param) return -EINVAL; /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ arg = 1; break; case PIN_CONFIG_DRIVE_STRENGTH: { unsigned int index; if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); /* * Drive strenght mA is supported only by group A and only * for 3V3 port source. */ arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; break; } case PIN_CONFIG_DRIVE_STRENGTH_UA: { enum rzg2l_iolh_index iolh_idx; u8 val; if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || !hwcfg->drive_strength_ua) return -EINVAL; ret = rzg2l_get_power_source(pctrl, _pin, cfg); if (ret < 0) return ret; iolh_idx = rzg2l_ps_to_iolh_idx(ret); val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); break; } case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { unsigned int index; if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = hwcfg->iolh_groupb_oi[index]; break; } case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); break; default: return -ENOTSUPP; } *config = pinconf_to_config_packed(param, arg); return 0; }; static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *_configs, unsigned int num_configs) { … } static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *configs, unsigned int num_configs) { const unsigned int *pins; unsigned int i, npins; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, num_configs); if (ret) return ret; } return 0; }; static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { const unsigned int *pins; unsigned int i, npins, prev_config = 0; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); if (ret) return ret; /* Check config matching between to pin */ if (i && prev_config != *config) return -EOPNOTSUPP; prev_config = *config; } return 0; }; static const struct pinctrl_ops rzg2l_pinctrl_pctlops = …; static const struct pinmux_ops rzg2l_pinctrl_pmxops = …; static const struct pinconf_ops rzg2l_pinctrl_confops = …; static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { … } static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, bool output) { … } static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static int rzg2l_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { … } static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { … } static int rzg2l_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { … } static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { … } static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) { … } static const char * const rzg2l_gpio_names[] = …; static const u64 r9a07g044_gpio_configs[] = …; static const u64 r9a07g043_gpio_configs[] = …; static const u64 r9a08g045_gpio_configs[] = …; static const char * const rzv2h_gpio_names[] = …; static const u64 r9a09g057_gpio_configs[] = …; static const struct { … } rzg2l_dedicated_pins = …; static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = …; static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = …; static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { … } static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, unsigned int hwirq, bool enable) { … } static void rzg2l_gpio_irq_disable(struct irq_data *d) { … } static void rzg2l_gpio_irq_enable(struct irq_data *d) { … } static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) { … } static void rzg2l_gpio_irqc_eoi(struct irq_data *d) { … } static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) { … } static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) { … } static const struct irq_chip rzg2l_gpio_irqchip = …; static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) { … } static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned int child, unsigned int child_type, unsigned int *parent, unsigned int *parent_type) { … } static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, union gpio_irq_fwspec *gfwspec, unsigned int parent_hwirq, unsigned int parent_type) { … } static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) { … } static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { … } static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, unsigned long *valid_mask, unsigned int ngpios) { … } static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) { … } static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) { … } static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) { … } static int rzg2l_pinctrl_probe(struct platform_device *pdev) { … } static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) { … } static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) { … } static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) { … } static int rzg2l_pinctrl_suspend_noirq(struct device *dev) { … } static int rzg2l_pinctrl_resume_noirq(struct device *dev) { … } static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) { … } static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) { … } static const struct rzg2l_hwcfg rzg2l_hwcfg = …; static const struct rzg2l_hwcfg rzg3s_hwcfg = …; static const struct rzg2l_hwcfg rzv2h_hwcfg = …; static struct rzg2l_pinctrl_data r9a07g043_data = …; static struct rzg2l_pinctrl_data r9a07g044_data = …; static struct rzg2l_pinctrl_data r9a08g045_data = …; static struct rzg2l_pinctrl_data r9a09g057_data = …; static const struct of_device_id rzg2l_pinctrl_of_table[] = …; static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = …; static struct platform_driver rzg2l_pinctrl_driver = …; static int __init rzg2l_pinctrl_init(void) { … } core_initcall(rzg2l_pinctrl_init); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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