// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) Maxime Coquelin 2015 * Copyright (C) STMicroelectronics 2017 * Author: Maxime Coquelin <[email protected]> * * Heavily based on Mediatek's pinctrl driver */ #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/hwspinlock.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/seq_file.h> #include <linux/slab.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" #include "pinctrl-stm32.h" #define STM32_GPIO_MODER … #define STM32_GPIO_TYPER … #define STM32_GPIO_SPEEDR … #define STM32_GPIO_PUPDR … #define STM32_GPIO_IDR … #define STM32_GPIO_ODR … #define STM32_GPIO_BSRR … #define STM32_GPIO_LCKR … #define STM32_GPIO_AFRL … #define STM32_GPIO_AFRH … #define STM32_GPIO_SECCFGR … /* custom bitfield to backup pin status */ #define STM32_GPIO_BKP_MODE_SHIFT … #define STM32_GPIO_BKP_MODE_MASK … #define STM32_GPIO_BKP_ALT_SHIFT … #define STM32_GPIO_BKP_ALT_MASK … #define STM32_GPIO_BKP_SPEED_SHIFT … #define STM32_GPIO_BKP_SPEED_MASK … #define STM32_GPIO_BKP_PUPD_SHIFT … #define STM32_GPIO_BKP_PUPD_MASK … #define STM32_GPIO_BKP_TYPE … #define STM32_GPIO_BKP_VAL … #define STM32_GPIO_PINS_PER_BANK … #define STM32_GPIO_IRQ_LINE … #define SYSCFG_IRQMUX_MASK … #define gpio_range_to_bank(chip) … #define HWSPNLCK_TIMEOUT … static const char * const stm32_gpio_functions[] = …; struct stm32_pinctrl_group { … }; struct stm32_gpio_bank { … }; struct stm32_pinctrl { … }; static inline int stm32_gpio_pin(int gpio) { … } static inline u32 stm32_gpio_get_mode(u32 function) { … } static inline u32 stm32_gpio_get_alt(u32 function) { … } static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, u32 offset, u32 value) { … } static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, u32 mode, u32 alt) { … } static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, u32 drive) { … } static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, u32 speed) { … } static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, u32 bias) { … } /* GPIO functions */ static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, unsigned offset, int value) { … } static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) { … } static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) { … } static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { … } static int stm32_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { … } static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) { … } static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static int stm32_gpio_init_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) { … } static const struct gpio_chip stm32_gpio_template = …; static void stm32_gpio_irq_trigger(struct irq_data *d) { … } static void stm32_gpio_irq_eoi(struct irq_data *d) { irq_chip_eoi_parent(d); stm32_gpio_irq_trigger(d); }; static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) { struct stm32_gpio_bank *bank = d->domain->host_data; u32 parent_type; switch (type) { case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_BOTH: parent_type = type; break; case IRQ_TYPE_LEVEL_HIGH: parent_type = IRQ_TYPE_EDGE_RISING; break; case IRQ_TYPE_LEVEL_LOW: parent_type = IRQ_TYPE_EDGE_FALLING; break; default: return -EINVAL; } bank->irq_type[d->hwirq] = type; return irq_chip_set_type_parent(d, parent_type); }; static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) { … } static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) { … } static void stm32_gpio_irq_unmask(struct irq_data *d) { … } static struct irq_chip stm32_gpio_irq_chip = …; static int stm32_gpio_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) { … } static int stm32_gpio_domain_activate(struct irq_domain *d, struct irq_data *irq_data, bool reserve) { … } static int stm32_gpio_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs, void *data) { … } static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs) { … } static const struct irq_domain_ops stm32_gpio_domain_ops = …; /* Pinctrl functions */ static struct stm32_pinctrl_group * stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) { … } static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, u32 pin_num, u32 fnum) { … } static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps) { … } static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *node, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps) { … } static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps) { … } static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) { … } static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, unsigned group) { … } static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, const unsigned **pins, unsigned *num_pins) { … } static const struct pinctrl_ops stm32_pctrl_ops = …; /* Pinmux functions */ static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) { … } static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, unsigned selector) { … } static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, unsigned function, const char * const **groups, unsigned * const num_groups) { … } static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, int pin, u32 mode, u32 alt) { … } void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt) { … } static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned group) { … } static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned gpio, bool input) { … } static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) { … } static const struct pinmux_ops stm32_pmx_ops = …; /* Pinconf functions */ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, unsigned offset, u32 drive) { … } static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, unsigned int offset) { … } static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, unsigned offset, u32 speed) { … } static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, unsigned int offset) { … } static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, unsigned offset, u32 bias) { … } static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, unsigned int offset) { … } static bool stm32_pconf_get(struct stm32_gpio_bank *bank, unsigned int offset, bool dir) { … } static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param, enum pin_config_param arg) { … } static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, unsigned long *config) { … } static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long *configs, unsigned num_configs) { … } static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { … } static struct stm32_desc_pin * stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, unsigned int pin_number) { … } static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) { … } static const struct pinconf_ops stm32_pconf_ops = …; static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, struct stm32_gpio_bank *bank, unsigned int offset) { … } static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) { … } static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev) { … } static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, struct stm32_pinctrl *pctl) { … } static int stm32_pctrl_build_state(struct platform_device *pdev) { … } static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, struct stm32_desc_pin *pins) { … } int stm32_pctl_probe(struct platform_device *pdev) { … } static int __maybe_unused stm32_pinctrl_restore_gpio_regs( struct stm32_pinctrl *pctl, u32 pin) { … } int __maybe_unused stm32_pinctrl_suspend(struct device *dev) { … } int __maybe_unused stm32_pinctrl_resume(struct device *dev) { … }
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