/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright(c) 2019 Intel Corporation. */ #ifndef __PINCTRL_EQUILIBRIUM_H #define __PINCTRL_EQUILIBRIUM_H /* PINPAD register offset */ #define REG_PMX_BASE … #define REG_PUEN … #define REG_PDEN … #define REG_SRC … #define REG_DCC0 … #define REG_DCC1 … #define REG_OD … #define REG_AVAIL … #define DRV_CUR_PINS … #define REG_DRCC(x) … /* GPIO register offset */ #define GPIO_OUT … #define GPIO_IN … #define GPIO_DIR … #define GPIO_EXINTCR0 … #define GPIO_EXINTCR1 … #define GPIO_IRNCR … #define GPIO_IRNICR … #define GPIO_IRNEN … #define GPIO_IRNCFG … #define GPIO_IRNRNSET … #define GPIO_IRNENCLR … #define GPIO_OUTSET … #define GPIO_OUTCLR … #define GPIO_DIRSET … #define GPIO_DIRCLR … /* parse given pin's driver current value */ #define PARSE_DRV_CURRENT(val, pin) … #define GPIO_EDGE_TRIG … #define GPIO_LEVEL_TRIG … #define GPIO_SINGLE_EDGE … #define GPIO_BOTH_EDGE … #define GPIO_POSITIVE_TRIG … #define GPIO_NEGATIVE_TRIG … #define EQBR_GPIO_MODE … funcs_util_ops; /** * struct gpio_irq_type: gpio irq configuration * @trig_type: level trigger or edge trigger * @edge_type: sigle edge or both edge * @logic_type: positive trigger or negative trigger */ struct gpio_irq_type { … }; /** * struct eqbr_pin_bank: represent a pin bank. * @membase: base address of the pin bank register. * @id: bank id, to idenify the unique bank. * @pin_base: starting pin number of the pin bank. * @nr_pins: number of the pins of the pin bank. * @aval_pinmap: available pin bitmap of the pin bank. */ struct eqbr_pin_bank { … }; struct fwnode_handle; /** * struct eqbr_gpio_ctrl: represent a gpio controller. * @chip: gpio chip. * @fwnode: firmware node of gpio controller. * @bank: pointer to corresponding pin bank. * @membase: base address of the gpio controller. * @name: gpio chip name. * @virq: irq number of the gpio chip to parent's irq domain. * @lock: spin lock to protect gpio register write. */ struct eqbr_gpio_ctrl { … }; /** * struct eqbr_pinctrl_drv_data: * @dev: device instance representing the controller. * @pctl_desc: pin controller descriptor. * @pctl_dev: pin control class device * @membase: base address of pin controller * @pin_banks: list of pin banks of the driver. * @nr_banks: number of pin banks. * @gpio_ctrls: list of gpio controllers. * @nr_gpio_ctrls: number of gpio controllers. * @lock: protect pinctrl register write */ struct eqbr_pinctrl_drv_data { … }; #endif /* __PINCTRL_EQUILIBRIUM_H */
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