// SPDX-License-Identifier: GPL-2.0-only /* * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support * * Copyright (C) 2022 9elements GmbH * Authors: Patrick Rudolph <[email protected]> * Naresh Solanki <[email protected]> */ #include <linux/acpi.h> #include <linux/bitmap.h> #include <linux/cleanup.h> #include <linux/dmi.h> #include <linux/gpio/driver.h> #include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/seq_file.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> /* Fast access registers */ #define CY8C95X0_INPUT … #define CY8C95X0_OUTPUT … #define CY8C95X0_INTSTATUS … #define CY8C95X0_INPUT_(x) … #define CY8C95X0_OUTPUT_(x) … #define CY8C95X0_INTSTATUS_(x) … /* Port Select configures the port */ #define CY8C95X0_PORTSEL … /* Port settings, write PORTSEL first */ #define CY8C95X0_INTMASK … #define CY8C95X0_PWMSEL … #define CY8C95X0_INVERT … #define CY8C95X0_DIRECTION … /* Drive mode register change state on writing '1' */ #define CY8C95X0_DRV_PU … #define CY8C95X0_DRV_PD … #define CY8C95X0_DRV_ODH … #define CY8C95X0_DRV_ODL … #define CY8C95X0_DRV_PP_FAST … #define CY8C95X0_DRV_PP_SLOW … #define CY8C95X0_DRV_HIZ … #define CY8C95X0_DEVID … #define CY8C95X0_WATCHDOG … #define CY8C95X0_COMMAND … #define CY8C95X0_PIN_TO_OFFSET(x) … #define MAX_BANK … #define BANK_SZ … #define MAX_LINE … #define MUXED_STRIDE … #define CY8C95X0_GPIO_MASK … #define CY8C95X0_VIRTUAL … #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) … static const struct i2c_device_id cy8c95x0_id[] = …; MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); #define OF_CY8C95X(__nrgpio) … static const struct of_device_id cy8c95x0_dt_ids[] = …; MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); static const struct acpi_gpio_params cy8c95x0_irq_gpios = …; static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = …; static int cy8c95x0_acpi_get_irq(struct device *dev) { … } static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = …; /** * struct cy8c95x0_pinctrl - driver data * @regmap: Device's regmap. Only direct access registers. * @irq_lock: IRQ bus lock * @i2c_lock: Mutex to hold while using the regmap * @irq_mask: I/O bits affected by interrupts * @irq_trig_raise: I/O bits affected by raising voltage level * @irq_trig_fall: I/O bits affected by falling voltage level * @irq_trig_low: I/O bits affected by a low voltage level * @irq_trig_high: I/O bits affected by a high voltage level * @push_pull: I/O bits configured as push pull driver * @shiftmask: Mask used to compensate for Gport2 width * @nport: Number of Gports in this chip * @gpio_chip: gpiolib chip * @driver_data: private driver data * @regulator: Pointer to the regulator for the IC * @dev: struct device * @pctldev: pin controller device * @pinctrl_desc: pin controller description * @name: Chip controller name * @tpin: Total number of pins * @gpio_reset: GPIO line handler that can reset the IC */ struct cy8c95x0_pinctrl { … }; static const struct pinctrl_pin_desc cy8c9560_pins[] = …; static const char * const cy8c95x0_groups[] = …; static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input); static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) { … } static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) { … } static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) { … } static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) { … } static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) { … } static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) { … } static bool cy8c95x0_muxed_register(unsigned int reg) { … } static bool cy8c95x0_wc_register(unsigned int reg) { … } static bool cy8c95x0_quick_path_register(unsigned int reg) { … } static const struct regmap_range_cfg cy8c95x0_ranges[] = …; static const struct regmap_config cy8c9520_i2c_regmap = …; static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, unsigned int reg, unsigned int port, unsigned int mask, unsigned int val, bool *change, bool async, bool force) { … } /** * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache * @chip: The pinctrl to work on * @reg: The register to write to. Can be direct access or muxed register. * MUST NOT be the PORTSEL register. * @port: The port to be used for muxed registers or quick path direct access * registers. Otherwise unused. * @mask: Bitmask to change * @val: New value for bitmask * * This function handles the register writes to the direct access registers and * the muxed registers while caching all register accesses, internally handling * the correct state of the PORTSEL register and protecting the access to muxed * registers. * The caller must only use this function to change registers behind the PORTSEL mux. * * Return: 0 for successful request, else a corresponding error value */ static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, unsigned int port, unsigned int mask, unsigned int val) { … } /** * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache * @chip: The pinctrl to work on * @reg: The register to write to. Can be direct access or muxed register. * MUST NOT be the PORTSEL register. * @port: The port to be used for muxed registers or quick path direct access * registers. Otherwise unused. * @mask: Bitmask to change * @val: New value for bitmask * * This function handles the register updates to the direct access registers and * the muxed registers while caching all register accesses, internally handling * the correct state of the PORTSEL register and protecting the access to muxed * registers. * The caller must only use this function to change registers behind the PORTSEL mux. * * Return: 0 for successful request, else a corresponding error value */ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, unsigned int port, unsigned int mask, unsigned int val) { … } /** * cy8c95x0_regmap_read() - reads a register using the regmap cache * @chip: The pinctrl to work on * @reg: The register to read from. Can be direct access or muxed register. * @port: The port to be used for muxed registers or quick path direct access * registers. Otherwise unused. * @read_val: Value read from hardware or cache * * This function handles the register reads from the direct access registers and * the muxed registers while caching all register accesses, internally handling * the correct state of the PORTSEL register and protecting the access to muxed * registers. * The caller must only use this function to read registers behind the PORTSEL mux. * * Return: 0 for successful request, else a corresponding error value */ static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, unsigned int port, unsigned int *read_val) { … } static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, unsigned long *val, unsigned long *mask) { … } static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, unsigned long *val, unsigned long *mask) { … } static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) { … } static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, unsigned int off, int val) { … } static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) { … } static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, int val) { … } static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) { … } static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, unsigned int off, unsigned long *config) { … } static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, unsigned int off, unsigned long config) { … } static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { … } static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { … } static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) { … } static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) { … } static void cy8c95x0_irq_mask(struct irq_data *d) { … } static void cy8c95x0_irq_unmask(struct irq_data *d) { … } static void cy8c95x0_irq_bus_lock(struct irq_data *d) { … } static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) { … } static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) { … } static void cy8c95x0_irq_shutdown(struct irq_data *d) { … } static const struct irq_chip cy8c95x0_irqchip = …; static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) { … } static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) { … } static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { … } static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) { … } static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { … } static const char *cy8c95x0_get_fname(unsigned int selector) { … } static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) { … } static const struct pinctrl_ops cy8c95x0_pinctrl_ops = …; static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) { … } static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) { … } static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, const char * const **groups, unsigned int * const num_groups) { … } static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) { … } static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, unsigned int selector, unsigned int group) { … } static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { … } static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) { … } static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input) { … } static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) { … } static const struct pinmux_ops cy8c95x0_pmxops = …; static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { … } static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { … } static const struct pinconf_ops cy8c95x0_pinconf_ops = …; static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) { … } static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) { … } static int cy8c95x0_detect(struct i2c_client *client, struct i2c_board_info *info) { … } static int cy8c95x0_probe(struct i2c_client *client) { … } static void cy8c95x0_remove(struct i2c_client *client) { … } static const struct acpi_device_id cy8c95x0_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); static struct i2c_driver cy8c95x0_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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