/* SPDX-License-Identifier: GPL-2.0-only */ /************************************************************************** * Copyright (c) 2007-2011, Intel Corporation. * All Rights Reserved. * **************************************************************************/ #ifndef _PSB_DRV_H_ #define _PSB_DRV_H_ #include <linux/kref.h> #include <linux/mm_types.h> #include <drm/drm_device.h> #include "gtt.h" #include "intel_bios.h" #include "mmu.h" #include "oaktrail.h" #include "opregion.h" #include "power.h" #include "psb_intel_drv.h" #include "psb_reg.h" #define DRIVER_AUTHOR … #define DRIVER_NAME … #define DRIVER_DESC … #define DRIVER_DATE … #define DRIVER_MAJOR … #define DRIVER_MINOR … #define DRIVER_PATCHLEVEL … /* Append new drm mode definition here, align with libdrm definition */ #define DRM_MODE_SCALE_NO_SCALE … #define IS_PSB(drm) … #define IS_MRST(drm) … #define IS_CDV(drm) … /* Hardware offsets */ #define PSB_VDC_OFFSET … #define PSB_VDC_SIZE … #define MRST_MMIO_SIZE … #define PSB_SGX_SIZE … #define PSB_SGX_OFFSET … #define MRST_SGX_OFFSET … /* PCI resource identifiers */ #define PSB_MMIO_RESOURCE … #define PSB_AUX_RESOURCE … #define PSB_GATT_RESOURCE … #define PSB_GTT_RESOURCE … /* PCI configuration */ #define PSB_GMCH_CTRL … #define PSB_BSM … #define _PSB_GMCH_ENABLED … #define PSB_PGETBL_CTL … #define _PSB_PGETBL_ENABLED … #define PSB_SGX_2D_SLAVE_PORT … #define PSB_LPC_GBA … /* TODO: To get rid of */ #define PSB_TT_PRIV0_LIMIT … #define PSB_TT_PRIV0_PLIMIT … /* SGX side MMU definitions (these can probably go) */ /* Flags for external memory type field */ #define PSB_MMU_CACHED_MEMORY … #define PSB_MMU_RO_MEMORY … #define PSB_MMU_WO_MEMORY … /* PTE's and PDE's */ #define PSB_PDE_MASK … #define PSB_PDE_SHIFT … #define PSB_PTE_SHIFT … /* Cache control */ #define PSB_PTE_VALID … #define PSB_PTE_WO … #define PSB_PTE_RO … #define PSB_PTE_CACHED … /* VDC registers and bits */ #define PSB_MSVDX_CLOCKGATING … #define PSB_TOPAZ_CLOCKGATING … #define PSB_HWSTAM … #define PSB_INSTPM … #define PSB_INT_IDENTITY_R … #define _PSB_IRQ_ASLE … #define _MDFLD_PIPEC_EVENT_FLAG … #define _MDFLD_PIPEC_VBLANK_FLAG … #define _PSB_DPST_PIPEB_FLAG … #define _MDFLD_PIPEB_EVENT_FLAG … #define _PSB_VSYNC_PIPEB_FLAG … #define _PSB_DPST_PIPEA_FLAG … #define _PSB_PIPEA_EVENT_FLAG … #define _PSB_VSYNC_PIPEA_FLAG … #define _PSB_IRQ_DISP_HOTSYNC … #define _PSB_IRQ_SGX_FLAG … #define _PSB_IRQ_MSVDX_FLAG … #define _LNC_IRQ_TOPAZ_FLAG … #define _PSB_PIPE_EVENT_FLAG … #define PSB_INT_IDENTITY_R … #define PSB_INT_MASK_R … #define PSB_INT_ENABLE_R … #define _PSB_MMU_ER_MASK … #define _PSB_MMU_ER_HOST … #define GPIOA … #define GPIOB … #define GPIOC … #define GPIOD … #define GPIOE … #define GPIOF … #define GPIOG … #define GPIOH … #define GPIO_CLOCK_DIR_MASK … #define GPIO_CLOCK_DIR_IN … #define GPIO_CLOCK_DIR_OUT … #define GPIO_CLOCK_VAL_MASK … #define GPIO_CLOCK_VAL_OUT … #define GPIO_CLOCK_VAL_IN … #define GPIO_CLOCK_PULLUP_DISABLE … #define GPIO_DATA_DIR_MASK … #define GPIO_DATA_DIR_IN … #define GPIO_DATA_DIR_OUT … #define GPIO_DATA_VAL_MASK … #define GPIO_DATA_VAL_OUT … #define GPIO_DATA_VAL_IN … #define GPIO_DATA_PULLUP_DISABLE … #define VCLK_DIVISOR_VGA0 … #define VCLK_DIVISOR_VGA1 … #define VCLK_POST_DIV … #define PSB_COMM_2D … #define PSB_COMM_3D … #define PSB_COMM_TA … #define PSB_COMM_HP … #define PSB_COMM_USER_IRQ … #define PSB_COMM_USER_IRQ_LOST … #define PSB_COMM_FW … #define PSB_UIRQ_VISTEST … #define PSB_UIRQ_OOM_REPLY … #define PSB_UIRQ_FIRE_TA_REPLY … #define PSB_UIRQ_FIRE_RASTER_REPLY … #define PSB_2D_SIZE … #define PSB_MAX_RELOC_PAGES … #define PSB_LOW_REG_OFFS … #define PSB_HIGH_REG_OFFS … #define PSB_NUM_VBLANKS … #define PSB_WATCHDOG_DELAY … #define PSB_MAX_BRIGHTNESS … #define PSB_PWR_STATE_ON … #define PSB_PWR_STATE_OFF … #define PSB_PMPOLICY_NOPM … #define PSB_PMPOLICY_CLOCKGATING … #define PSB_PMPOLICY_POWERDOWN … #define PSB_PMSTATE_POWERUP … #define PSB_PMSTATE_CLOCKGATED … #define PSB_PMSTATE_POWERDOWN … #define PSB_PCIx_MSI_ADDR_LOC … #define PSB_PCIx_MSI_DATA_LOC … /* Medfield crystal settings */ #define KSEL_CRYSTAL_19 … #define KSEL_BYPASS_19 … #define KSEL_BYPASS_25 … #define KSEL_BYPASS_83_100 … struct opregion_header; struct opregion_acpi; struct opregion_swsci; struct opregion_asle; struct psb_intel_opregion { … }; struct sdvo_device_mapping { … }; struct intel_gmbus { … }; /* Register offset maps */ struct psb_offset { … }; /* * Register save state. This is used to hold the context when the * device is powered off. In the case of Oaktrail this can (but does not * yet) include screen blank. Operations occuring during the save * update the register cache instead. */ /* Common status for pipes */ struct psb_pipe { … }; struct psb_state { … }; struct cdv_state { … }; struct psb_save_area { … }; struct psb_ops; #define PSB_NUM_PIPE … struct intel_scu_ipc_dev; struct drm_psb_private { … }; static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev) { … } /* Operations for each board type */ struct psb_ops { … }; /* modesetting */ extern void psb_modeset_init(struct drm_device *dev); extern void psb_modeset_cleanup(struct drm_device *dev); /* framebuffer */ struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj); /* fbdev */ #if defined(CONFIG_DRM_FBDEV_EMULATION) void psb_fbdev_setup(struct drm_psb_private *dev_priv); #else static inline void psb_fbdev_setup(struct drm_psb_private *dev_priv) { } #endif /* backlight.c */ int gma_backlight_init(struct drm_device *dev); void gma_backlight_exit(struct drm_device *dev); void gma_backlight_disable(struct drm_device *dev); void gma_backlight_enable(struct drm_device *dev); void gma_backlight_set(struct drm_device *dev, int v); /* oaktrail_crtc.c */ extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; /* oaktrail_lvds.c */ extern void oaktrail_lvds_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev); /* psb_intel_display.c */ extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; /* psb_intel_lvds.c */ extern const struct drm_connector_helper_funcs psb_intel_lvds_connector_helper_funcs; extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; /* gem.c */ extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args); /* psb_device.c */ extern const struct psb_ops psb_chip_ops; /* oaktrail_device.c */ extern const struct psb_ops oaktrail_chip_ops; /* cdv_device.c */ extern const struct psb_ops cdv_chip_ops; /* Utilities */ static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) { … } static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) { … } #define REG_READ(reg) … #define REG_READ_AUX(reg) … /* Useful for post reads */ static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, uint32_t reg, int aux) { … } #define REG_READ_WITH_AUX(reg, aux) … static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, uint32_t val) { … } static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, uint32_t val) { … } #define REG_WRITE(reg, val) … #define REG_WRITE_AUX(reg, val) … static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, uint32_t val, int aux) { … } #define REG_WRITE_WITH_AUX(reg, val, aux) … static inline void REGISTER_WRITE16(struct drm_device *dev, uint32_t reg, uint32_t val) { … } #define REG_WRITE16(reg, val) … static inline void REGISTER_WRITE8(struct drm_device *dev, uint32_t reg, uint32_t val) { … } #define REG_WRITE8(reg, val) … #define PSB_WVDC32(_val, _offs) … #define PSB_RVDC32(_offs) … #define PSB_RSGX32(_offs) … #define PSB_WSGX32(_val, _offs) … #define PSB_WMSVDX32(_val, _offs) … #define PSB_RMSVDX32(_offs) … #endif
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