// SPDX-License-Identifier: GPL-2.0-only /* * Copyright © 2006-2011 Intel Corporation * * Authors: * Eric Anholt <[email protected]> */ #include <linux/delay.h> #include <linux/i2c.h> #include <drm/drm_crtc.h> #include <drm/drm_modeset_helper_vtables.h> #include "cdv_device.h" #include "framebuffer.h" #include "gma_display.h" #include "power.h" #include "psb_drv.h" #include "psb_intel_drv.h" #include "psb_intel_reg.h" static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock); #define CDV_LIMIT_SINGLE_LVDS_96 … #define CDV_LIMIT_SINGLE_LVDS_100 … #define CDV_LIMIT_DAC_HDMI_27 … #define CDV_LIMIT_DAC_HDMI_96 … #define CDV_LIMIT_DP_27 … #define CDV_LIMIT_DP_100 … static const struct gma_limit_t cdv_intel_limits[] = …; #define _wait_for(COND, MS, W) … #define wait_for(COND, MS) … int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) { … } int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) { … } /* Reset the DPIO configuration register. The BIOS does this at every * mode set. */ void cdv_sb_reset(struct drm_device *dev) { … } /* Unlike most Intel display engines, on Cedarview the DPLL registers * are behind this sideband bus. They must be programmed while the * DPLL reference clock is on in the DPLL control register, but before * the DPLL is enabled in the DPLL control register. */ static int cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) { … } static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc, int refclk) { … } /* m1 is reserved as 0 in CDV, n is a ring counter */ static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) { … } static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock) { … } #define FIFO_PIPEA … #define FIFO_PIPEB … static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe) { … } void cdv_disable_sr(struct drm_device *dev) { … } void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc) { … } /* * Return the pipe currently connected to the panel fitter, * or -1 if the panel fitter is not present or not in use */ static int cdv_intel_panel_fitter_pipe(struct drm_device *dev) { … } static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, int x, int y, struct drm_framebuffer *old_fb) { … } /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ /* FIXME: why are we using this, should it be cdv_ in this tree ? */ static void i8xx_clock(int refclk, struct gma_clock_t *clock) { … } /* Returns the clock of the currently programmed mode of the given pipe. */ static int cdv_intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) { … } /** Returns the currently programmed mode of the given pipe. */ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, struct drm_crtc *crtc) { … } const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = …; const struct gma_clock_funcs cdv_clock_funcs = …;
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