linux/drivers/gpu/drm/sun4i/sun4i_hdmi.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (C) 2016 Maxime Ripard
 *
 * Maxime Ripard <[email protected]>
 */

#ifndef _SUN4I_HDMI_H_
#define _SUN4I_HDMI_H_

#include <drm/drm_connector.h>
#include <drm/drm_encoder.h>
#include <linux/regmap.h>

#include <media/cec-pin.h>

#define SUN4I_HDMI_CTRL_REG
#define SUN4I_HDMI_CTRL_ENABLE

#define SUN4I_HDMI_IRQ_REG
#define SUN4I_HDMI_IRQ_STA_MASK
#define SUN4I_HDMI_IRQ_STA_FIFO_OF
#define SUN4I_HDMI_IRQ_STA_FIFO_UF

#define SUN4I_HDMI_HPD_REG
#define SUN4I_HDMI_HPD_HIGH

#define SUN4I_HDMI_VID_CTRL_REG
#define SUN4I_HDMI_VID_CTRL_ENABLE
#define SUN4I_HDMI_VID_CTRL_HDMI_MODE

#define SUN4I_HDMI_VID_TIMING_ACT_REG
#define SUN4I_HDMI_VID_TIMING_BP_REG
#define SUN4I_HDMI_VID_TIMING_FP_REG
#define SUN4I_HDMI_VID_TIMING_SPW_REG

#define SUN4I_HDMI_VID_TIMING_X(x)
#define SUN4I_HDMI_VID_TIMING_Y(y)

#define SUN4I_HDMI_VID_TIMING_POL_REG
#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK
#define SUN4I_HDMI_VID_TIMING_POL_VSYNC
#define SUN4I_HDMI_VID_TIMING_POL_HSYNC

#define SUN4I_HDMI_AVI_INFOFRAME_REG(n)

#define SUN4I_HDMI_PAD_CTRL0_REG
#define SUN4I_HDMI_PAD_CTRL0_BIASEN
#define SUN4I_HDMI_PAD_CTRL0_LDOCEN
#define SUN4I_HDMI_PAD_CTRL0_LDODEN
#define SUN4I_HDMI_PAD_CTRL0_PWENC
#define SUN4I_HDMI_PAD_CTRL0_PWEND
#define SUN4I_HDMI_PAD_CTRL0_PWENG
#define SUN4I_HDMI_PAD_CTRL0_CKEN
#define SUN4I_HDMI_PAD_CTRL0_TXEN

#define SUN4I_HDMI_PAD_CTRL1_REG
#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN
#define SUN4I_HDMI_PAD_CTRL1_AMP_OPT
#define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT
#define SUN4I_HDMI_PAD_CTRL1_EMP_OPT
#define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT
#define SUN4I_HDMI_PAD_CTRL1_PWSCK
#define SUN4I_HDMI_PAD_CTRL1_PWSDT
#define SUN4I_HDMI_PAD_CTRL1_REG_DEN
#define SUN4I_HDMI_PAD_CTRL1_REG_DENCK
#define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)
#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK
#define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n)

/* These bits seem to invert the TMDS data channels */
#define SUN4I_HDMI_PAD_CTRL1_INVERT_R
#define SUN4I_HDMI_PAD_CTRL1_INVERT_G
#define SUN4I_HDMI_PAD_CTRL1_INVERT_B

#define SUN4I_HDMI_PLL_CTRL_REG
#define SUN4I_HDMI_PLL_CTRL_PLL_EN
#define SUN4I_HDMI_PLL_CTRL_BWS
#define SUN4I_HDMI_PLL_CTRL_HV_IS_33
#define SUN4I_HDMI_PLL_CTRL_LDO1_EN
#define SUN4I_HDMI_PLL_CTRL_LDO2_EN
#define SUN4I_HDMI_PLL_CTRL_SDIV2
#define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n)
#define SUN4I_HDMI_PLL_CTRL_S(n)
#define SUN4I_HDMI_PLL_CTRL_CP_S(n)
#define SUN4I_HDMI_PLL_CTRL_CS(n)
#define SUN4I_HDMI_PLL_CTRL_DIV(n)
#define SUN4I_HDMI_PLL_CTRL_DIV_MASK
#define SUN4I_HDMI_PLL_CTRL_VCO_S(n)

#define SUN4I_HDMI_PLL_DBG0_REG
#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n)
#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK
#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT

#define SUN4I_HDMI_CEC
#define SUN4I_HDMI_CEC_ENABLE
#define SUN4I_HDMI_CEC_TX
#define SUN4I_HDMI_CEC_RX

#define SUN4I_HDMI_PKT_CTRL_REG(n)
#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t)

#define SUN4I_HDMI_UNKNOWN_REG
#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC

#define SUN4I_HDMI_DDC_CTRL_REG
#define SUN4I_HDMI_DDC_CTRL_ENABLE
#define SUN4I_HDMI_DDC_CTRL_START_CMD
#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK
#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE
#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ
#define SUN4I_HDMI_DDC_CTRL_RESET

#define SUN4I_HDMI_DDC_ADDR_REG
#define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg)
#define SUN4I_HDMI_DDC_ADDR_EDDC(addr)
#define SUN4I_HDMI_DDC_ADDR_OFFSET(off)
#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr)

#define SUN4I_HDMI_DDC_INT_STATUS_REG
#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION
#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW
#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW
#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST
#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR
#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR
#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR
#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE

#define SUN4I_HDMI_DDC_FIFO_CTRL_REG
#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR
#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n)
#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK
#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX
#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n)
#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK
#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX

#define SUN4I_HDMI_DDC_FIFO_DATA_REG

#define SUN4I_HDMI_DDC_BYTE_COUNT_REG
#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX

#define SUN4I_HDMI_DDC_CMD_REG
#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ
#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ
#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE

#define SUN4I_HDMI_DDC_CLK_REG
#define SUN4I_HDMI_DDC_CLK_M(m)
#define SUN4I_HDMI_DDC_CLK_N(n)

#define SUN4I_HDMI_DDC_LINE_CTRL_REG
#define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE
#define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE

#define SUN4I_HDMI_DDC_FIFO_SIZE

/* A31 specific */
#define SUN6I_HDMI_DDC_CTRL_REG
#define SUN6I_HDMI_DDC_CTRL_RESET
#define SUN6I_HDMI_DDC_CTRL_START_CMD
#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE
#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE
#define SUN6I_HDMI_DDC_CTRL_ENABLE

#define SUN6I_HDMI_DDC_CMD_REG
#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count)
/* command types in lower 3 bits are the same as sun4i */

#define SUN6I_HDMI_DDC_ADDR_REG
#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg)
#define SUN6I_HDMI_DDC_ADDR_EDDC(addr)
#define SUN6I_HDMI_DDC_ADDR_OFFSET(off)
#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr)

#define SUN6I_HDMI_DDC_INT_STATUS_REG
#define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT
/* lower 8 bits are the same as sun4i */

#define SUN6I_HDMI_DDC_FIFO_CTRL_REG
#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR
/* lower 9 bits are the same as sun4i */

#define SUN6I_HDMI_DDC_CLK_REG
/* DDC CLK bit fields are the same, but the formula is not */

#define SUN6I_HDMI_DDC_FIFO_DATA_REG

enum sun4i_hdmi_pkt_type {};

struct sun4i_hdmi_variant {};

struct sun4i_hdmi {};

int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi);

#endif /* _SUN4I_HDMI_H_ */