linux/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2018 Jernej Skrabec <[email protected]>
 */

#ifndef _SUN8I_DW_HDMI_H_
#define _SUN8I_DW_HDMI_H_

#include <drm/bridge/dw_hdmi.h>
#include <drm/drm_encoder.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>

#define SUN8I_HDMI_PHY_DBG_CTRL_REG
#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK
#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK
#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC
#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC
#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK
#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr)

#define SUN8I_HDMI_PHY_REXT_CTRL_REG
#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN

#define SUN8I_HDMI_PHY_READ_EN_REG
#define SUN8I_HDMI_PHY_READ_EN_MAGIC

#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG
#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC

#define SUN8I_HDMI_PHY_ANA_CFG1_REG
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x)
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x)
#define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT
#define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT
#define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT
#define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT
#define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL
#define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG
#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS
#define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN
#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK
#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL
#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK
#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2
#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1
#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0
#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK
#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2
#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1
#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0
#define SUN8I_HDMI_PHY_ANA_CFG1_CKEN
#define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN
#define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS
#define SUN8I_HDMI_PHY_ANA_CFG1_ENBI

#define SUN8I_HDMI_PHY_ANA_CFG2_REG
#define SUN8I_HDMI_PHY_ANA_CFG2_M_EN
#define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN
#define SUN8I_HDMI_PHY_ANA_CFG2_SEN
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x)
#define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x)

#define SUN8I_HDMI_PHY_ANA_CFG3_REG
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x)
#define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD
#define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN
#define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD
#define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN

#define SUN8I_HDMI_PHY_PLL_CFG1_REG
#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1
#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN
#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33
#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK
#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT
#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)
#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x)
#define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN
#define SUN8I_HDMI_PHY_PLL_CFG1_CS
#define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x)
#define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x)
#define SUN8I_HDMI_PHY_PLL_CFG1_BWS
#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK
#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT

#define SUN8I_HDMI_PHY_PLL_CFG2_REG
#define SUN8I_HDMI_PHY_PLL_CFG2_SV_H
#define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x)
#define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x)
#define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x)
#define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL
#define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS
#define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN
#define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN
#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN
#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x)
#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x)
#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN
#define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC
#define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2
#define SUN8I_HDMI_PHY_PLL_CFG2_S(x)
#define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5
#define SUN8I_HDMI_PHY_PLL_CFG2_S5_7
#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK
#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT
#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x)

#define SUN8I_HDMI_PHY_PLL_CFG3_REG
#define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2

#define SUN8I_HDMI_PHY_ANA_STS_REG
#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT
#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK
#define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D
#define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK

#define SUN8I_HDMI_PHY_CEC_REG

struct sun8i_hdmi_phy;

struct sun8i_hdmi_phy_variant {};

struct sun8i_hdmi_phy {};

struct sun8i_dw_hdmi_quirks {};

struct sun8i_dw_hdmi {};

extern struct platform_driver sun8i_hdmi_phy_driver;

static inline struct sun8i_dw_hdmi *
encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
{}

int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node);

int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy);
void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
			    struct dw_hdmi_plat_data *plat_data);

int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
			 bool second_parent);

#endif /* _SUN8I_DW_HDMI_H_ */