/* * Copyright (C) 2013 Red Hat * Author: Rob Clark <[email protected]> * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef __MSM_DRM_H__ #define __MSM_DRM_H__ #include "drm.h" #if defined(__cplusplus) extern "C" { #endif /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints: * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit * user/kernel compatibility * 2) Keep fields aligned to their size * 3) Because of how drm_ioctl() works, we can add new fields at * the end of an ioctl if some care is taken: drm_ioctl() will * zero out the new fields at the tail of the ioctl, so a zero * value should have a backwards compatible meaning. And for * output params, userspace won't see the newly added output * fields.. so that has to be somehow ok. */ #define MSM_PIPE_NONE … #define MSM_PIPE_2D0 … #define MSM_PIPE_2D1 … #define MSM_PIPE_3D0 … /* The pipe-id just uses the lower bits, so can be OR'd with flags in * the upper 16 bits (which could be extended further, if needed, maybe * we extend/overload the pipe-id some day to deal with multiple rings, * but even then I don't think we need the full lower 16 bits). */ #define MSM_PIPE_ID_MASK … #define MSM_PIPE_ID(x) … #define MSM_PIPE_FLAGS(x) … /* timeouts are specified in clock-monotonic absolute times (to simplify * restarting interrupted ioctls). The following struct is logically the * same as 'struct timespec' but 32/64b ABI safe. */ struct drm_msm_timespec { … }; /* Below "RO" indicates a read-only param, "WO" indicates write-only, and * "RW" indicates a param that can be both read (GET_PARAM) and written * (SET_PARAM) */ #define MSM_PARAM_GPU_ID … #define MSM_PARAM_GMEM_SIZE … #define MSM_PARAM_CHIP_ID … #define MSM_PARAM_MAX_FREQ … #define MSM_PARAM_TIMESTAMP … #define MSM_PARAM_GMEM_BASE … #define MSM_PARAM_PRIORITIES … #define MSM_PARAM_PP_PGTABLE … #define MSM_PARAM_FAULTS … #define MSM_PARAM_SUSPENDS … #define MSM_PARAM_SYSPROF … #define MSM_PARAM_COMM … #define MSM_PARAM_CMDLINE … #define MSM_PARAM_VA_START … #define MSM_PARAM_VA_SIZE … #define MSM_PARAM_HIGHEST_BANK_BIT … #define MSM_PARAM_RAYTRACING … #define MSM_PARAM_UBWC_SWIZZLE … #define MSM_PARAM_MACROTILE_MODE … /* For backwards compat. The original support for preemption was based on * a single ring per priority level so # of priority levels equals the # * of rings. With drm/scheduler providing additional levels of priority, * the number of priorities is greater than the # of rings. The param is * renamed to better reflect this. */ #define MSM_PARAM_NR_RINGS … struct drm_msm_param { … }; /* * GEM buffers: */ #define MSM_BO_SCANOUT … #define MSM_BO_GPU_READONLY … #define MSM_BO_CACHE_MASK … /* cache modes */ #define MSM_BO_CACHED … #define MSM_BO_WC … #define MSM_BO_UNCACHED … #define MSM_BO_CACHED_COHERENT … #define MSM_BO_FLAGS … struct drm_msm_gem_new { … }; /* Get or set GEM buffer info. The requested value can be passed * directly in 'value', or for data larger than 64b 'value' is a * pointer to userspace buffer, with 'len' specifying the number of * bytes copied into that buffer. For info returned by pointer, * calling the GEM_INFO ioctl with null 'value' will return the * required buffer size in 'len' */ #define MSM_INFO_GET_OFFSET … #define MSM_INFO_GET_IOVA … #define MSM_INFO_SET_NAME … #define MSM_INFO_GET_NAME … #define MSM_INFO_SET_IOVA … #define MSM_INFO_GET_FLAGS … #define MSM_INFO_SET_METADATA … #define MSM_INFO_GET_METADATA … struct drm_msm_gem_info { … }; #define MSM_PREP_READ … #define MSM_PREP_WRITE … #define MSM_PREP_NOSYNC … #define MSM_PREP_BOOST … #define MSM_PREP_FLAGS … struct drm_msm_gem_cpu_prep { … }; struct drm_msm_gem_cpu_fini { … }; /* * Cmdstream Submission: */ /* The value written into the cmdstream is logically: * * ((relocbuf->gpuaddr + reloc_offset) << shift) | or * * When we have GPU's w/ >32bit ptrs, it should be possible to deal * with this by emit'ing two reloc entries with appropriate shift * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. * * NOTE that reloc's must be sorted by order of increasing submit_offset, * otherwise EINVAL. */ struct drm_msm_gem_submit_reloc { … }; /* submit-types: * BUF - this cmd buffer is executed normally. * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are * processed normally, but the kernel does not setup an IB to * this buffer in the first-level ringbuffer * CTX_RESTORE_BUF - only executed if there has been a GPU context * switch since the last SUBMIT ioctl */ #define MSM_SUBMIT_CMD_BUF … #define MSM_SUBMIT_CMD_IB_TARGET_BUF … #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF … struct drm_msm_gem_submit_cmd { … }; /* Each buffer referenced elsewhere in the cmdstream submit (ie. the * cmdstream buffer(s) themselves or reloc entries) has one (and only * one) entry in the submit->bos[] table. * * As a optimization, the current buffer (gpu virtual address) can be * passed back through the 'presumed' field. If on a subsequent reloc, * userspace passes back a 'presumed' address that is still valid, * then patching the cmdstream for this entry is skipped. This can * avoid kernel needing to map/access the cmdstream bo in the common * case. */ #define MSM_SUBMIT_BO_READ … #define MSM_SUBMIT_BO_WRITE … #define MSM_SUBMIT_BO_DUMP … #define MSM_SUBMIT_BO_NO_IMPLICIT … #define MSM_SUBMIT_BO_FLAGS … struct drm_msm_gem_submit_bo { … }; /* Valid submit ioctl flags: */ #define MSM_SUBMIT_NO_IMPLICIT … #define MSM_SUBMIT_FENCE_FD_IN … #define MSM_SUBMIT_FENCE_FD_OUT … #define MSM_SUBMIT_SUDO … #define MSM_SUBMIT_SYNCOBJ_IN … #define MSM_SUBMIT_SYNCOBJ_OUT … #define MSM_SUBMIT_FENCE_SN_IN … #define MSM_SUBMIT_FLAGS … #define MSM_SUBMIT_SYNCOBJ_RESET … #define MSM_SUBMIT_SYNCOBJ_FLAGS … struct drm_msm_gem_submit_syncobj { … }; /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ struct drm_msm_gem_submit { … }; #define MSM_WAIT_FENCE_BOOST … #define MSM_WAIT_FENCE_FLAGS … /* The normal way to synchronize with the GPU is just to CPU_PREP on * a buffer if you need to access it from the CPU (other cmdstream * submission from same or other contexts, PAGE_FLIP ioctl, etc, all * handle the required synchronization under the hood). This ioctl * mainly just exists as a way to implement the gallium pipe_fence * APIs without requiring a dummy bo to synchronize on. */ struct drm_msm_wait_fence { … }; /* madvise provides a way to tell the kernel in case a buffers contents * can be discarded under memory pressure, which is useful for userspace * bo cache where we want to optimistically hold on to buffer allocate * and potential mmap, but allow the pages to be discarded under memory * pressure. * * Typical usage would involve madvise(DONTNEED) when buffer enters BO * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. * In the WILLNEED case, 'retained' indicates to userspace whether the * backing pages still exist. */ #define MSM_MADV_WILLNEED … #define MSM_MADV_DONTNEED … #define __MSM_MADV_PURGED … struct drm_msm_gem_madvise { … }; /* * Draw queues allow the user to set specific submission parameter. Command * submissions specify a specific submitqueue to use. ID 0 is reserved for * backwards compatibility as a "default" submitqueue */ #define MSM_SUBMITQUEUE_FLAGS … /* * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, * a lower numeric value is higher priority. */ struct drm_msm_submitqueue { … }; #define MSM_SUBMITQUEUE_PARAM_FAULTS … struct drm_msm_submitqueue_query { … }; #define DRM_MSM_GET_PARAM … #define DRM_MSM_SET_PARAM … #define DRM_MSM_GEM_NEW … #define DRM_MSM_GEM_INFO … #define DRM_MSM_GEM_CPU_PREP … #define DRM_MSM_GEM_CPU_FINI … #define DRM_MSM_GEM_SUBMIT … #define DRM_MSM_WAIT_FENCE … #define DRM_MSM_GEM_MADVISE … /* placeholder: #define DRM_MSM_GEM_SVM_NEW 0x09 */ #define DRM_MSM_SUBMITQUEUE_NEW … #define DRM_MSM_SUBMITQUEUE_CLOSE … #define DRM_MSM_SUBMITQUEUE_QUERY … #define DRM_IOCTL_MSM_GET_PARAM … #define DRM_IOCTL_MSM_SET_PARAM … #define DRM_IOCTL_MSM_GEM_NEW … #define DRM_IOCTL_MSM_GEM_INFO … #define DRM_IOCTL_MSM_GEM_CPU_PREP … #define DRM_IOCTL_MSM_GEM_CPU_FINI … #define DRM_IOCTL_MSM_GEM_SUBMIT … #define DRM_IOCTL_MSM_WAIT_FENCE … #define DRM_IOCTL_MSM_GEM_MADVISE … #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW … #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE … #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY … #if defined(__cplusplus) } #endif #endif /* __MSM_DRM_H__ */
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