/* SPDX-License-Identifier: GPL-2.0 */ // // Ingenic JZ47xx KMS driver - Register definitions and private API // // Copyright (C) 2020, Paul Cercueil <[email protected]> #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H #include <linux/bitops.h> #include <linux/types.h> #define JZ_REG_LCD_CFG … #define JZ_REG_LCD_VSYNC … #define JZ_REG_LCD_HSYNC … #define JZ_REG_LCD_VAT … #define JZ_REG_LCD_DAH … #define JZ_REG_LCD_DAV … #define JZ_REG_LCD_PS … #define JZ_REG_LCD_CLS … #define JZ_REG_LCD_SPL … #define JZ_REG_LCD_REV … #define JZ_REG_LCD_CTRL … #define JZ_REG_LCD_STATE … #define JZ_REG_LCD_IID … #define JZ_REG_LCD_DA0 … #define JZ_REG_LCD_SA0 … #define JZ_REG_LCD_FID0 … #define JZ_REG_LCD_CMD0 … #define JZ_REG_LCD_DA1 … #define JZ_REG_LCD_SA1 … #define JZ_REG_LCD_FID1 … #define JZ_REG_LCD_CMD1 … #define JZ_REG_LCD_RGBC … #define JZ_REG_LCD_OSDC … #define JZ_REG_LCD_OSDCTRL … #define JZ_REG_LCD_OSDS … #define JZ_REG_LCD_BGC … #define JZ_REG_LCD_KEY0 … #define JZ_REG_LCD_KEY1 … #define JZ_REG_LCD_ALPHA … #define JZ_REG_LCD_IPUR … #define JZ_REG_LCD_XYP0 … #define JZ_REG_LCD_XYP1 … #define JZ_REG_LCD_SIZE0 … #define JZ_REG_LCD_SIZE1 … #define JZ_REG_LCD_PCFG … #define JZ_LCD_CFG_SLCD … #define JZ_LCD_CFG_DESCRIPTOR_8 … #define JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN … #define JZ_LCD_CFG_PS_DISABLE … #define JZ_LCD_CFG_CLS_DISABLE … #define JZ_LCD_CFG_SPL_DISABLE … #define JZ_LCD_CFG_REV_DISABLE … #define JZ_LCD_CFG_HSYNCM … #define JZ_LCD_CFG_PCLKM … #define JZ_LCD_CFG_INV … #define JZ_LCD_CFG_SYNC_DIR … #define JZ_LCD_CFG_PS_POLARITY … #define JZ_LCD_CFG_CLS_POLARITY … #define JZ_LCD_CFG_SPL_POLARITY … #define JZ_LCD_CFG_REV_POLARITY … #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW … #define JZ_LCD_CFG_PCLK_FALLING_EDGE … #define JZ_LCD_CFG_DE_ACTIVE_LOW … #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW … #define JZ_LCD_CFG_18_BIT … #define JZ_LCD_CFG_24_BIT … #define JZ_LCD_CFG_PDW … #define JZ_LCD_CFG_MODE_GENERIC_16BIT … #define JZ_LCD_CFG_MODE_GENERIC_18BIT … #define JZ_LCD_CFG_MODE_GENERIC_24BIT … #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 … #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 … #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 … #define JZ_LCD_CFG_MODE_TV_OUT_P … #define JZ_LCD_CFG_MODE_TV_OUT_I … #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN … #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN … #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN … #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN … #define JZ_LCD_CFG_MODE_8BIT_SERIAL … #define JZ_LCD_CFG_MODE_LCM … #define JZ_LCD_VSYNC_VPS_OFFSET … #define JZ_LCD_VSYNC_VPE_OFFSET … #define JZ_LCD_HSYNC_HPS_OFFSET … #define JZ_LCD_HSYNC_HPE_OFFSET … #define JZ_LCD_VAT_HT_OFFSET … #define JZ_LCD_VAT_VT_OFFSET … #define JZ_LCD_DAH_HDS_OFFSET … #define JZ_LCD_DAH_HDE_OFFSET … #define JZ_LCD_DAV_VDS_OFFSET … #define JZ_LCD_DAV_VDE_OFFSET … #define JZ_LCD_CTRL_BURST_4 … #define JZ_LCD_CTRL_BURST_8 … #define JZ_LCD_CTRL_BURST_16 … #define JZ_LCD_CTRL_BURST_32 … #define JZ_LCD_CTRL_BURST_64 … #define JZ_LCD_CTRL_BURST_MASK … #define JZ_LCD_CTRL_RGB555 … #define JZ_LCD_CTRL_OFUP … #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 … #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 … #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 … #define JZ_LCD_CTRL_PDD_MASK … #define JZ_LCD_CTRL_EOF_IRQ … #define JZ_LCD_CTRL_SOF_IRQ … #define JZ_LCD_CTRL_OFU_IRQ … #define JZ_LCD_CTRL_IFU0_IRQ … #define JZ_LCD_CTRL_IFU1_IRQ … #define JZ_LCD_CTRL_DD_IRQ … #define JZ_LCD_CTRL_QDD_IRQ … #define JZ_LCD_CTRL_REVERSE_ENDIAN … #define JZ_LCD_CTRL_LSB_FISRT … #define JZ_LCD_CTRL_DISABLE … #define JZ_LCD_CTRL_ENABLE … #define JZ_LCD_CTRL_BPP_1 … #define JZ_LCD_CTRL_BPP_2 … #define JZ_LCD_CTRL_BPP_4 … #define JZ_LCD_CTRL_BPP_8 … #define JZ_LCD_CTRL_BPP_15_16 … #define JZ_LCD_CTRL_BPP_18_24 … #define JZ_LCD_CTRL_BPP_24_COMP … #define JZ_LCD_CTRL_BPP_30 … #define JZ_LCD_CTRL_BPP_MASK … #define JZ_LCD_CMD_SOF_IRQ … #define JZ_LCD_CMD_EOF_IRQ … #define JZ_LCD_CMD_ENABLE_PAL … #define JZ_LCD_CMD_FRM_ENABLE … #define JZ_LCD_SYNC_MASK … #define JZ_LCD_STATE_EOF_IRQ … #define JZ_LCD_STATE_SOF_IRQ … #define JZ_LCD_STATE_DISABLED … #define JZ_LCD_RGBC_ODD_RGB … #define JZ_LCD_RGBC_ODD_RBG … #define JZ_LCD_RGBC_ODD_GRB … #define JZ_LCD_RGBC_ODD_GBR … #define JZ_LCD_RGBC_ODD_BRG … #define JZ_LCD_RGBC_ODD_BGR … #define JZ_LCD_RGBC_EVEN_RGB … #define JZ_LCD_RGBC_EVEN_RBG … #define JZ_LCD_RGBC_EVEN_GRB … #define JZ_LCD_RGBC_EVEN_GBR … #define JZ_LCD_RGBC_EVEN_BRG … #define JZ_LCD_RGBC_EVEN_BGR … #define JZ_LCD_OSDC_OSDEN … #define JZ_LCD_OSDC_ALPHAEN … #define JZ_LCD_OSDC_F0EN … #define JZ_LCD_OSDC_F1EN … #define JZ_LCD_OSDCTRL_IPU … #define JZ_LCD_OSDCTRL_RGB555 … #define JZ_LCD_OSDCTRL_CHANGE … #define JZ_LCD_OSDCTRL_BPP_15_16 … #define JZ_LCD_OSDCTRL_BPP_18_24 … #define JZ_LCD_OSDCTRL_BPP_24_COMP … #define JZ_LCD_OSDCTRL_BPP_30 … #define JZ_LCD_OSDCTRL_BPP_MASK … #define JZ_LCD_OSDS_READY … #define JZ_LCD_IPUR_IPUREN … #define JZ_LCD_IPUR_IPUR_LSB … #define JZ_LCD_XYP01_XPOS_LSB … #define JZ_LCD_XYP01_YPOS_LSB … #define JZ_LCD_SIZE01_WIDTH_LSB … #define JZ_LCD_SIZE01_HEIGHT_LSB … #define JZ_LCD_DESSIZE_ALPHA_OFFSET … #define JZ_LCD_DESSIZE_HEIGHT_MASK … #define JZ_LCD_DESSIZE_WIDTH_MASK … #define JZ_LCD_CPOS_BPP_15_16 … #define JZ_LCD_CPOS_BPP_18_24 … #define JZ_LCD_CPOS_BPP_30 … #define JZ_LCD_CPOS_RGB555 … #define JZ_LCD_CPOS_PREMULTIPLY_LCD … #define JZ_LCD_CPOS_COEFFICIENT_OFFSET … #define JZ_LCD_CPOS_COEFFICIENT_0 … #define JZ_LCD_CPOS_COEFFICIENT_1 … #define JZ_LCD_CPOS_COEFFICIENT_ALPHA1 … #define JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 … #define JZ_LCD_RGBC_RGB_PADDING … #define JZ_LCD_RGBC_RGB_PADDING_FIRST … #define JZ_LCD_RGBC_422 … #define JZ_LCD_RGBC_RGB_FORMAT_ENABLE … #define JZ_LCD_PCFG_PRI_MODE … #define JZ_LCD_PCFG_HP_BST_4 … #define JZ_LCD_PCFG_HP_BST_8 … #define JZ_LCD_PCFG_HP_BST_16 … #define JZ_LCD_PCFG_HP_BST_32 … #define JZ_LCD_PCFG_HP_BST_64 … #define JZ_LCD_PCFG_HP_BST_16_CONT … #define JZ_LCD_PCFG_HP_BST_DISABLE … #define JZ_LCD_PCFG_THRESHOLD2_OFFSET … #define JZ_LCD_PCFG_THRESHOLD1_OFFSET … #define JZ_LCD_PCFG_THRESHOLD0_OFFSET … struct device; struct drm_plane; struct drm_plane_state; struct platform_driver; void ingenic_drm_plane_config(struct device *dev, struct drm_plane *plane, u32 fourcc); void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); bool ingenic_drm_map_noncoherent(const struct device *dev); extern struct platform_driver *ingenic_ipu_driver_ptr; #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */
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