#ifndef STATE_HI_XML #define STATE_HI_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng headergen tool in this git repository: http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - state.xml ( 29355 bytes, from 2024-01-19 10:18:54) - common.xml ( 35664 bytes, from 2023-12-06 10:55:32) - common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) - state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17) - copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) - state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03) - state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54) - state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09) - state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan <[email protected]> - Christian Gmeiner <[email protected]> - Lucas Stach <[email protected]> - Russell King <[email protected]> Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define MMU_EXCEPTION_SLAVE_NOT_PRESENT … #define MMU_EXCEPTION_PAGE_NOT_PRESENT … #define MMU_EXCEPTION_WRITE_VIOLATION … #define MMU_EXCEPTION_OUT_OF_BOUND … #define MMU_EXCEPTION_READ_SECURITY_VIOLATION … #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION … #define VIVS_HI … #define VIVS_HI_CLOCK_CONTROL … #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS … #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS … #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK … #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT … #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) … #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD … #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING … #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS … #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET … #define VIVS_HI_CLOCK_CONTROL_IDLE_3D … #define VIVS_HI_CLOCK_CONTROL_IDLE_2D … #define VIVS_HI_CLOCK_CONTROL_IDLE_VG … #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU … #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK … #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT … #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) … #define VIVS_HI_IDLE_STATE … #define VIVS_HI_IDLE_STATE_FE … #define VIVS_HI_IDLE_STATE_DE … #define VIVS_HI_IDLE_STATE_PE … #define VIVS_HI_IDLE_STATE_SH … #define VIVS_HI_IDLE_STATE_PA … #define VIVS_HI_IDLE_STATE_SE … #define VIVS_HI_IDLE_STATE_RA … #define VIVS_HI_IDLE_STATE_TX … #define VIVS_HI_IDLE_STATE_VG … #define VIVS_HI_IDLE_STATE_IM … #define VIVS_HI_IDLE_STATE_FP … #define VIVS_HI_IDLE_STATE_TS … #define VIVS_HI_IDLE_STATE_BL … #define VIVS_HI_IDLE_STATE_ASYNCFE … #define VIVS_HI_IDLE_STATE_MC … #define VIVS_HI_IDLE_STATE_PPA … #define VIVS_HI_IDLE_STATE_WD … #define VIVS_HI_IDLE_STATE_NN … #define VIVS_HI_IDLE_STATE_TP … #define VIVS_HI_IDLE_STATE_AXI_LP … #define VIVS_HI_AXI_CONFIG … #define VIVS_HI_AXI_CONFIG_AWID__MASK … #define VIVS_HI_AXI_CONFIG_AWID__SHIFT … #define VIVS_HI_AXI_CONFIG_AWID(x) … #define VIVS_HI_AXI_CONFIG_ARID__MASK … #define VIVS_HI_AXI_CONFIG_ARID__SHIFT … #define VIVS_HI_AXI_CONFIG_ARID(x) … #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK … #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT … #define VIVS_HI_AXI_CONFIG_AWCACHE(x) … #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK … #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT … #define VIVS_HI_AXI_CONFIG_ARCACHE(x) … #define VIVS_HI_AXI_STATUS … #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK … #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT … #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) … #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK … #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT … #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) … #define VIVS_HI_AXI_STATUS_DET_WR_ERR … #define VIVS_HI_AXI_STATUS_DET_RD_ERR … #define VIVS_HI_INTR_ACKNOWLEDGE … #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK … #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT … #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) … #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION … #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR … #define VIVS_HI_INTR_ENBL … #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK … #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT … #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) … #define VIVS_HI_CHIP_IDENTITY … #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK … #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT … #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) … #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK … #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT … #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) … #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK … #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT … #define VIVS_HI_CHIP_IDENTITY_REVISION(x) … #define VIVS_HI_CHIP_FEATURE … #define VIVS_HI_CHIP_MODEL … #define VIVS_HI_CHIP_REV … #define VIVS_HI_CHIP_DATE … #define VIVS_HI_CHIP_TIME … #define VIVS_HI_CHIP_CUSTOMER_ID … #define VIVS_HI_CHIP_MINOR_FEATURE_0 … #define VIVS_HI_CACHE_CONTROL … #define VIVS_HI_MEMORY_COUNTER_RESET … #define VIVS_HI_PROFILE_READ_BYTES8 … #define VIVS_HI_PROFILE_WRITE_BYTES8 … #define VIVS_HI_CHIP_SPECS … #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) … #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK … #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT … #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) … #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) … #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK … #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT … #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) … #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) … #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK … #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT … #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) … #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK … #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT … #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) … #define VIVS_HI_PROFILE_WRITE_BURSTS … #define VIVS_HI_PROFILE_WRITE_REQUESTS … #define VIVS_HI_PROFILE_READ_BURSTS … #define VIVS_HI_PROFILE_READ_REQUESTS … #define VIVS_HI_PROFILE_READ_LASTS … #define VIVS_HI_GP_OUT0 … #define VIVS_HI_GP_OUT1 … #define VIVS_HI_GP_OUT2 … #define VIVS_HI_AXI_CONTROL … #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE … #define VIVS_HI_CHIP_MINOR_FEATURE_1 … #define VIVS_HI_PROFILE_TOTAL_CYCLES … #define VIVS_HI_PROFILE_IDLE_CYCLES … #define VIVS_HI_CHIP_SPECS_2 … #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK … #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT … #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) … #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) … #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK … #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT … #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) … #define VIVS_HI_CHIP_MINOR_FEATURE_2 … #define VIVS_HI_CHIP_MINOR_FEATURE_3 … #define VIVS_HI_CHIP_SPECS_3 … #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) … #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) … #define VIVS_HI_COMPRESSION_FLAGS … #define VIVS_HI_COMPRESSION_FLAGS_DEC300 … #define VIVS_HI_CHIP_MINOR_FEATURE_4 … #define VIVS_HI_CHIP_SPECS_4 … #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK … #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT … #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) … #define VIVS_HI_CHIP_MINOR_FEATURE_5 … #define VIVS_HI_CHIP_PRODUCT_ID … #define VIVS_HI_BLT_INTR … #define VIVS_HI_CHIP_ECO_ID … #define VIVS_HI_AUXBIT … #define VIVS_PM … #define VIVS_PM_POWER_CONTROLS … #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING … #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING … #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING … #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK … #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT … #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) … #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK … #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT … #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) … #define VIVS_PM_MODULE_CONTROLS … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ … #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN … #define VIVS_PM_MODULE_STATUS … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA … #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX … #define VIVS_PM_PULSE_EATER … #define VIVS_PM_PULSE_EATER_DISABLE … #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK … #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT … #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) … #define VIVS_PM_PULSE_EATER_UNK16 … #define VIVS_PM_PULSE_EATER_UNK17 … #define VIVS_PM_PULSE_EATER_INTERNAL_DFS … #define VIVS_PM_PULSE_EATER_UNK19 … #define VIVS_PM_PULSE_EATER_UNK20 … #define VIVS_PM_PULSE_EATER_UNK22 … #define VIVS_PM_PULSE_EATER_UNK23 … #define VIVS_MMUv2 … #define VIVS_MMUv2_SAFE_ADDRESS … #define VIVS_MMUv2_CONFIGURATION … #define VIVS_MMUv2_CONFIGURATION_MODE__MASK … #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT … #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K … #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K … #define VIVS_MMUv2_CONFIGURATION_MODE_MASK … #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK … #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT … #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH … #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK … #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK … #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK … #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT … #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) … #define VIVS_MMUv2_STATUS … #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK … #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT … #define VIVS_MMUv2_STATUS_EXCEPTION0(x) … #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK … #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT … #define VIVS_MMUv2_STATUS_EXCEPTION1(x) … #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK … #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT … #define VIVS_MMUv2_STATUS_EXCEPTION2(x) … #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK … #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT … #define VIVS_MMUv2_STATUS_EXCEPTION3(x) … #define VIVS_MMUv2_CONTROL … #define VIVS_MMUv2_CONTROL_ENABLE … #define VIVS_MMUv2_EXCEPTION_ADDR(i0) … #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE … #define VIVS_MMUv2_EXCEPTION_ADDR__LEN … #define VIVS_MMUv2_PROFILE_BLT_READ … #define VIVS_MMUv2_PTA_CONFIG … #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK … #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT … #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) … #define VIVS_MMUv2_PTA_CONFIG_UNK16 … #define VIVS_MMUv2_AXI_POLICY(i0) … #define VIVS_MMUv2_AXI_POLICY__ESIZE … #define VIVS_MMUv2_AXI_POLICY__LEN … #define VIVS_MMUv2_SEC_EXCEPTION_ADDR … #define VIVS_MMUv2_SEC_STATUS … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT … #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) … #define VIVS_MMUv2_SEC_CONTROL … #define VIVS_MMUv2_SEC_CONTROL_ENABLE … #define VIVS_MMUv2_PTA_ADDRESS_LOW … #define VIVS_MMUv2_PTA_ADDRESS_HIGH … #define VIVS_MMUv2_PTA_CONTROL … #define VIVS_MMUv2_PTA_CONTROL_ENABLE … #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW … #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) … #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 … #define VIVS_MMUv2_SEC_COMMAND_CONTROL … #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK … #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT … #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) … #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE … #define VIVS_MMUv2_AHB_CONTROL … #define VIVS_MMUv2_AHB_CONTROL_RESET … #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS … #define VIVS_MC … #define VIVS_MC_MMU_FE_PAGE_TABLE … #define VIVS_MC_MMU_TX_PAGE_TABLE … #define VIVS_MC_MMU_PE_PAGE_TABLE … #define VIVS_MC_MMU_PEZ_PAGE_TABLE … #define VIVS_MC_MMU_RA_PAGE_TABLE … #define VIVS_MC_DEBUG_MEMORY … #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 … #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS … #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS … #define VIVS_MC_MEMORY_BASE_ADDR_RA … #define VIVS_MC_MEMORY_BASE_ADDR_FE … #define VIVS_MC_MEMORY_BASE_ADDR_TX … #define VIVS_MC_MEMORY_BASE_ADDR_PEZ … #define VIVS_MC_MEMORY_BASE_ADDR_PE … #define VIVS_MC_MEMORY_TIMING_CONTROL … #define VIVS_MC_MEMORY_FLUSH … #define VIVS_MC_PROFILE_CYCLE_COUNTER … #define VIVS_MC_DEBUG_READ0 … #define VIVS_MC_DEBUG_READ1 … #define VIVS_MC_DEBUG_WRITE … #define VIVS_MC_PROFILE_RA_READ … #define VIVS_MC_PROFILE_TX_READ … #define VIVS_MC_PROFILE_FE_READ … #define VIVS_MC_PROFILE_PE_READ … #define VIVS_MC_PROFILE_DE_READ … #define VIVS_MC_PROFILE_SH_READ … #define VIVS_MC_PROFILE_PA_READ … #define VIVS_MC_PROFILE_SE_READ … #define VIVS_MC_PROFILE_MC_READ … #define VIVS_MC_PROFILE_HI_READ … #define VIVS_MC_PROFILE_CONFIG0 … #define VIVS_MC_PROFILE_CONFIG0_FE__MASK … #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT … #define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT … #define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT … #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT … #define VIVS_MC_PROFILE_CONFIG0_FE_RESET … #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_LK_COUNT … #define VIVS_MC_PROFILE_CONFIG0_FE_STALL_COUNT … #define VIVS_MC_PROFILE_CONFIG0_FE_PROCESS_COUNT … #define VIVS_MC_PROFILE_CONFIG0_DE__MASK … #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT … #define VIVS_MC_PROFILE_CONFIG0_DE_RESET … #define VIVS_MC_PROFILE_CONFIG0_PE__MASK … #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT … #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE … #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE … #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE … #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE … #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D … #define VIVS_MC_PROFILE_CONFIG0_PE_RESET … #define VIVS_MC_PROFILE_CONFIG0_SH__MASK … #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT … #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES … #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER … #define VIVS_MC_PROFILE_CONFIG0_SH_RESET … #define VIVS_MC_PROFILE_CONFIG1 … #define VIVS_MC_PROFILE_CONFIG1_PA__MASK … #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT … #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_DROPED_PRIM_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_FRUSTUM_CLIPPED_PRIM_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_PA_RESET … #define VIVS_MC_PROFILE_CONFIG1_SE__MASK … #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT … #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT … #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT … #define VIVS_MC_PROFILE_CONFIG1_SE_TRIVIAL_REJECTED_LINE_COUNT … #define VIVS_MC_PROFILE_CONFIG1_SE_RESET … #define VIVS_MC_PROFILE_CONFIG1_RA__MASK … #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT … #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT … #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT … #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z … #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT … #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT … #define VIVS_MC_PROFILE_CONFIG1_RA_RESET … #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_HZ_CACHE_MISS_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_HZ_CACHE_MISS_COUNTER … #define VIVS_MC_PROFILE_CONFIG1_TX__MASK … #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT … #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS … #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS … #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS … #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS … #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN … #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT … #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT … #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT … #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT … #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT … #define VIVS_MC_PROFILE_CONFIG1_TX_RESET … #define VIVS_MC_PROFILE_CONFIG2 … #define VIVS_MC_PROFILE_CONFIG2_MC__MASK … #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_COLORPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_COLORPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_DEPTHPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_SENTOUT_FROM_DEPTHPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_DEPTHPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_DEPTHPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_DEPTHPIPE … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_OTHERS … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_OTHERS … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_FROM_OTHERS … #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_OTHERS … #define VIVS_MC_PROFILE_CONFIG2_MC_FE_READ_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_MMU_READ_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_READ_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_READ_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_READ_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_PE_WRITE_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_WRITE_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_WRITE_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_WRITE_BANDWIDTH … #define VIVS_MC_PROFILE_CONFIG2_HI__MASK … #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT … #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED … #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED … #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED … #define VIVS_MC_PROFILE_CONFIG2_HI_RESET … #define VIVS_MC_PROFILE_CONFIG2_L2__MASK … #define VIVS_MC_PROFILE_CONFIG2_L2__SHIFT … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_READ_REQUEST_COUNT … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_WRITE_REQUEST_COUNT … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI1_WRITE_REQUEST_COUNT … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI0 … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI1 … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI0 … #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI1 … #define VIVS_MC_PROFILE_CONFIG2_L2_RESET … #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_MINMAX_LATENCY … #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_LATENCY … #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_REQUEST_COUNT … #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_MINMAX_LATENCY … #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_LATENCY … #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_REQUEST_COUNT … #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK … #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT … #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 … #define VIVS_MC_PROFILE_CONFIG3 … #define VIVS_MC_BUS_CONFIG … #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK … #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT … #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) … #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK … #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT … #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) … #define VIVS_MC_START_COMPOSITION … #define VIVS_MC_FLAGS … #define VIVS_MC_FLAGS_128B_MERGE … #define VIVS_MC_FLAGS_TPCV11_COMPRESSION … #define VIVS_MC_L2_CACHE_CONFIG … #define VIVS_MC_PROFILE_L2_READ … #define VIVS_MC_MC_LATENCY_RESET … #define VIVS_MC_MC_AXI_MAX_MIN_LATENCY … #define VIVS_MC_MC_AXI_TOTAL_LATENCY … #define VIVS_MC_MC_AXI_SAMPLE_COUNT … #define VIVS_DEC400EX … #define VIVS_DEC400EX_UNK00800 … #define VIVS_DEC400EX_UNK00808 … #endif /* STATE_HI_XML */
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