/* SPDX-License-Identifier: GPL-2.0-only */ /* * * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. * * Parts of this file were based on sources as follows: * * Copyright (c) 2006-2008 Intel Corporation * Copyright (c) 2007 Dave Airlie <[email protected]> * Copyright (C) 2011 Texas Instruments */ #ifndef _PL111_DRM_H_ #define _PL111_DRM_H_ #include <linux/clk-provider.h> #include <linux/interrupt.h> #include <drm/drm_bridge.h> #include <drm/drm_connector.h> #include <drm/drm_encoder.h> #include <drm/drm_gem.h> #include <drm/drm_panel.h> #include <drm/drm_simple_kms_helper.h> /* * CLCD Controller Internal Register addresses */ #define CLCD_TIM0 … #define CLCD_TIM1 … #define CLCD_TIM2 … #define CLCD_TIM3 … #define CLCD_UBAS … #define CLCD_LBAS … #define CLCD_PL110_IENB … #define CLCD_PL110_CNTL … #define CLCD_PL110_STAT … #define CLCD_PL110_INTR … #define CLCD_PL110_UCUR … #define CLCD_PL110_LCUR … #define CLCD_PL111_CNTL … #define CLCD_PL111_IENB … #define CLCD_PL111_RIS … #define CLCD_PL111_MIS … #define CLCD_PL111_ICR … #define CLCD_PL111_UCUR … #define CLCD_PL111_LCUR … #define CLCD_PALL … #define CLCD_PALETTE … #define TIM2_PCD_LO_MASK … #define TIM2_PCD_LO_BITS … #define TIM2_CLKSEL … #define TIM2_ACB_MASK … #define TIM2_IVS … #define TIM2_IHS … #define TIM2_IPC … #define TIM2_IOE … #define TIM2_BCD … #define TIM2_PCD_HI_MASK … #define TIM2_PCD_HI_BITS … #define TIM2_PCD_HI_SHIFT … #define CNTL_LCDEN … #define CNTL_LCDBPP1 … #define CNTL_LCDBPP2 … #define CNTL_LCDBPP4 … #define CNTL_LCDBPP8 … #define CNTL_LCDBPP16 … #define CNTL_LCDBPP16_565 … #define CNTL_LCDBPP16_444 … #define CNTL_LCDBPP24 … #define CNTL_LCDBW … #define CNTL_LCDTFT … #define CNTL_LCDMONO8 … #define CNTL_LCDDUAL … #define CNTL_BGR … #define CNTL_BEBO … #define CNTL_BEPO … #define CNTL_LCDPWR … #define CNTL_LCDVCOMP(x) … #define CNTL_LDMAFIFOTIME … #define CNTL_WATERMARK … /* ST Microelectronics variant bits */ #define CNTL_ST_1XBPP_444 … #define CNTL_ST_1XBPP_5551 … #define CNTL_ST_1XBPP_565 … #define CNTL_ST_CDWID_12 … #define CNTL_ST_CDWID_16 … #define CNTL_ST_CDWID_18 … #define CNTL_ST_CDWID_24 … #define CNTL_ST_CEAEN … #define CNTL_ST_LCDBPP24_PACKED … #define CLCD_IRQ_NEXTBASE_UPDATE … struct drm_minor; /** * struct pl111_variant_data - encodes IP differences * @name: the name of this variant * @is_pl110: this is the early PL110 variant * @is_lcdc: this is the ST Microelectronics Nomadik LCDC variant * @external_bgr: this is the Versatile Pl110 variant with external * BGR/RGB routing * @broken_clockdivider: the clock divider is broken and we need to * use the supplied clock directly * @broken_vblank: the vblank IRQ is broken on this variant * @st_bitmux_control: this variant is using the ST Micro bitmux * extensions to the control register * @formats: array of supported pixel formats on this variant * @nformats: the length of the array of supported pixel formats * @fb_depth: desired depth per pixel on the default framebuffer */ struct pl111_variant_data { … }; struct pl111_drm_dev_private { … }; int pl111_display_init(struct drm_device *dev); irqreturn_t pl111_irq(int irq, void *data); void pl111_debugfs_init(struct drm_minor *minor); #endif /* _PL111_DRM_H_ */
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