// SPDX-License-Identifier: GPL-2.0 /* * ZynqMP DisplayPort Driver * * Copyright (C) 2017 - 2020 Xilinx, Inc. * * Authors: * - Hyun Woo Kwon <[email protected]> * - Laurent Pinchart <[email protected]> */ #include <drm/display/drm_dp_helper.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_device.h> #include <drm/drm_edid.h> #include <drm/drm_fourcc.h> #include <drm/drm_modes.h> #include <drm/drm_of.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/io.h> #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/phy/phy.h> #include <linux/reset.h> #include <linux/slab.h> #include "zynqmp_disp.h" #include "zynqmp_dp.h" #include "zynqmp_dpsub.h" #include "zynqmp_kms.h" static uint zynqmp_dp_aux_timeout_ms = …; module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); MODULE_PARM_DESC(…) …; /* * Some sink requires a delay after power on request */ static uint zynqmp_dp_power_on_delay_ms = …; module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); MODULE_PARM_DESC(…) …; /* Link configuration registers */ #define ZYNQMP_DP_LINK_BW_SET … #define ZYNQMP_DP_LANE_COUNT_SET … #define ZYNQMP_DP_ENHANCED_FRAME_EN … #define ZYNQMP_DP_TRAINING_PATTERN_SET … #define ZYNQMP_DP_SCRAMBLING_DISABLE … #define ZYNQMP_DP_DOWNSPREAD_CTL … #define ZYNQMP_DP_SOFTWARE_RESET … #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1 … #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2 … #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3 … #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4 … #define ZYNQMP_DP_SOFTWARE_RESET_AUX … #define ZYNQMP_DP_SOFTWARE_RESET_ALL … /* Core enable registers */ #define ZYNQMP_DP_TRANSMITTER_ENABLE … #define ZYNQMP_DP_MAIN_STREAM_ENABLE … #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET … #define ZYNQMP_DP_VERSION … #define ZYNQMP_DP_VERSION_MAJOR_MASK … #define ZYNQMP_DP_VERSION_MAJOR_SHIFT … #define ZYNQMP_DP_VERSION_MINOR_MASK … #define ZYNQMP_DP_VERSION_MINOR_SHIFT … #define ZYNQMP_DP_VERSION_REVISION_MASK … #define ZYNQMP_DP_VERSION_REVISION_SHIFT … #define ZYNQMP_DP_VERSION_PATCH_MASK … #define ZYNQMP_DP_VERSION_PATCH_SHIFT … #define ZYNQMP_DP_VERSION_INTERNAL_MASK … #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT … /* Core ID registers */ #define ZYNQMP_DP_CORE_ID … #define ZYNQMP_DP_CORE_ID_MAJOR_MASK … #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT … #define ZYNQMP_DP_CORE_ID_MINOR_MASK … #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT … #define ZYNQMP_DP_CORE_ID_REVISION_MASK … #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT … #define ZYNQMP_DP_CORE_ID_DIRECTION … /* AUX channel interface registers */ #define ZYNQMP_DP_AUX_COMMAND … #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT … #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY … #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT … #define ZYNQMP_DP_AUX_WRITE_FIFO … #define ZYNQMP_DP_AUX_ADDRESS … #define ZYNQMP_DP_AUX_CLK_DIVIDER … #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT … #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE … #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD … #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST … #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY … #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT … #define ZYNQMP_DP_AUX_REPLY_DATA … #define ZYNQMP_DP_AUX_REPLY_CODE … #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK … #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK … #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER … #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK … #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK … #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER … #define ZYNQMP_DP_AUX_REPLY_COUNT … #define ZYNQMP_DP_REPLY_DATA_COUNT … #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK … #define ZYNQMP_DP_INT_STATUS … #define ZYNQMP_DP_INT_MASK … #define ZYNQMP_DP_INT_EN … #define ZYNQMP_DP_INT_DS … #define ZYNQMP_DP_INT_HPD_IRQ … #define ZYNQMP_DP_INT_HPD_EVENT … #define ZYNQMP_DP_INT_REPLY_RECEIVED … #define ZYNQMP_DP_INT_REPLY_TIMEOUT … #define ZYNQMP_DP_INT_HPD_PULSE_DET … #define ZYNQMP_DP_INT_EXT_PKT_TXD … #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW … #define ZYNQMP_DP_INT_VBLANK_START … #define ZYNQMP_DP_INT_PIXEL1_MATCH … #define ZYNQMP_DP_INT_PIXEL0_MATCH … #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK … #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK … #define ZYNQMP_DP_INT_CUST_TS_2 … #define ZYNQMP_DP_INT_CUST_TS … #define ZYNQMP_DP_INT_EXT_VSYNC_TS … #define ZYNQMP_DP_INT_VSYNC_TS … #define ZYNQMP_DP_INT_ALL … /* Main stream attribute registers */ #define ZYNQMP_DP_MAIN_STREAM_HTOTAL … #define ZYNQMP_DP_MAIN_STREAM_VTOTAL … #define ZYNQMP_DP_MAIN_STREAM_POLARITY … #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT … #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT … #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH … #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH … #define ZYNQMP_DP_MAIN_STREAM_HRES … #define ZYNQMP_DP_MAIN_STREAM_VRES … #define ZYNQMP_DP_MAIN_STREAM_HSTART … #define ZYNQMP_DP_MAIN_STREAM_VSTART … #define ZYNQMP_DP_MAIN_STREAM_MISC0 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK … #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB … #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK … #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE … #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR … #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16 … #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK … #define ZYNQMP_DP_MAIN_STREAM_MISC1 … #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN … #define ZYNQMP_DP_MAIN_STREAM_M_VID … #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE … #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF … #define ZYNQMP_DP_MAIN_STREAM_N_VID … #define ZYNQMP_DP_USER_PIX_WIDTH … #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE … #define ZYNQMP_DP_MIN_BYTES_PER_TU … #define ZYNQMP_DP_FRAC_BYTES_PER_TU … #define ZYNQMP_DP_INIT_WAIT … /* PHY configuration and status registers */ #define ZYNQMP_DP_PHY_RESET … #define ZYNQMP_DP_PHY_RESET_PHY_RESET … #define ZYNQMP_DP_PHY_RESET_GTTX_RESET … #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET … #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET … #define ZYNQMP_DP_PHY_RESET_ALL_RESET … #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0 … #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1 … #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2 … #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3 … #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0 … #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1 … #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2 … #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3 … #define ZYNQMP_DP_PHY_CLOCK_SELECT … #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G … #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G … #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G … #define ZYNQMP_DP_TX_PHY_POWER_DOWN … #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0 … #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1 … #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2 … #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3 … #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL … #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0 … #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1 … #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2 … #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3 … #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0 … #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1 … #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2 … #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3 … #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 … #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1 … #define ZYNQMP_DP_PHY_STATUS … #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT … #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED … /* Audio registers */ #define ZYNQMP_DP_TX_AUDIO_CONTROL … #define ZYNQMP_DP_TX_AUDIO_CHANNELS … #define ZYNQMP_DP_TX_AUDIO_INFO_DATA … #define ZYNQMP_DP_TX_M_AUD … #define ZYNQMP_DP_TX_N_AUD … #define ZYNQMP_DP_TX_AUDIO_EXT_DATA … #define ZYNQMP_DP_MAX_LANES … #define ZYNQMP_MAX_FREQ … #define DP_REDUCED_BIT_RATE … #define DP_HIGH_BIT_RATE … #define DP_HIGH_BIT_RATE2 … #define DP_MAX_TRAINING_TRIES … #define DP_V1_2 … /** * struct zynqmp_dp_link_config - Common link config between source and sink * @max_rate: maximum link rate * @max_lanes: maximum number of lanes */ struct zynqmp_dp_link_config { … }; /** * struct zynqmp_dp_mode - Configured mode of DisplayPort * @bw_code: code for bandwidth(link rate) * @lane_cnt: number of lanes * @pclock: pixel clock frequency of current mode * @fmt: format identifier string */ struct zynqmp_dp_mode { … }; /** * struct zynqmp_dp_config - Configuration of DisplayPort from DTS * @misc0: misc0 configuration (per DP v1.2 spec) * @misc1: misc1 configuration (per DP v1.2 spec) * @bpp: bits per pixel */ struct zynqmp_dp_config { … }; /** * struct zynqmp_dp - Xilinx DisplayPort core * @dev: device structure * @dpsub: Display subsystem * @iomem: device I/O memory for register access * @reset: reset controller * @irq: irq * @bridge: DRM bridge for the DP encoder * @next_bridge: The downstream bridge * @config: IP core configuration from DTS * @aux: aux channel * @phy: PHY handles for DP lanes * @num_lanes: number of enabled phy lanes * @hpd_work: hot plug detection worker * @status: connection status * @enabled: flag to indicate if the device is enabled * @dpcd: DP configuration data from currently connected sink device * @link_config: common link configuration between IP core and sink device * @mode: current mode between IP core and sink device * @train_set: set of training data */ struct zynqmp_dp { … }; static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge) { … } static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val) { … } static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset) { … } static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr) { … } static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set) { … } /* ----------------------------------------------------------------------------- * PHY Handling */ #define RST_TIMEOUT_MS … static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert) { … } /** * zynqmp_dp_phy_init - Initialize the phy * @dp: DisplayPort IP core structure * * Initialize the phy. * * Return: 0 if the phy instances are initialized correctly, or the error code * returned from the callee functions. */ static int zynqmp_dp_phy_init(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_phy_exit - Exit the phy * @dp: DisplayPort IP core structure * * Exit the phy. */ static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_phy_probe - Probe the PHYs * @dp: DisplayPort IP core structure * * Probe PHYs for all lanes. Less PHYs may be available than the number of * lanes, which is not considered an error as long as at least one PHY is * found. The caller can check dp->num_lanes to check how many PHYs were found. * * Return: * * 0 - Success * * -ENXIO - No PHY found * * -EPROBE_DEFER - Probe deferral requested * * Other negative value - PHY retrieval failure */ static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_phy_ready - Check if PHY is ready * @dp: DisplayPort IP core structure * * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. * This amount of delay was suggested by IP designer. * * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready. */ static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp) { … } /* ----------------------------------------------------------------------------- * DisplayPort Link Training */ /** * zynqmp_dp_max_rate - Calculate and return available max pixel clock * @link_rate: link rate (Kilo-bytes / sec) * @lane_num: number of lanes * @bpp: bits per pixel * * Return: max pixel clock (KHz) supported by current link config. */ static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp) { … } /** * zynqmp_dp_mode_configure - Configure the link values * @dp: DisplayPort IP core structure * @pclock: pixel clock for requested display mode * @current_bw: current link rate * * Find the link configuration values, rate and lane count for requested pixel * clock @pclock. The @pclock is stored in the mode to be used in other * functions later. The returned rate is downshifted from the current rate * @current_bw. * * Return: Current link rate code, or -EINVAL. */ static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, u8 current_bw) { … } /** * zynqmp_dp_adjust_train - Adjust train values * @dp: DisplayPort IP core structure * @link_status: link status from sink which contains requested training values */ static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp, u8 link_status[DP_LINK_STATUS_SIZE]) { … } /** * zynqmp_dp_update_vs_emph - Update the training values * @dp: DisplayPort IP core structure * * Update the training values based on the request from sink. The mapped values * are predefined, and values(vs, pe, pc) are from the device manual. * * Return: 0 if vs and emph are updated successfully, or the error code returned * by drm_dp_dpcd_write(). */ static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_link_train_cr - Train clock recovery * @dp: DisplayPort IP core structure * * Return: 0 if clock recovery train is done successfully, or corresponding * error code. */ static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_link_train_ce - Train channel equalization * @dp: DisplayPort IP core structure * * Return: 0 if channel equalization train is done successfully, or * corresponding error code. */ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_train - Train the link * @dp: DisplayPort IP core structure * * Return: 0 if all trains are done successfully, or corresponding error code. */ static int zynqmp_dp_train(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_train_loop - Downshift the link rate during training * @dp: DisplayPort IP core structure * * Train the link by downshifting the link rate if training is not successful. */ static void zynqmp_dp_train_loop(struct zynqmp_dp *dp) { … } /* ----------------------------------------------------------------------------- * DisplayPort AUX */ #define AUX_READ_BIT … /** * zynqmp_dp_aux_cmd_submit - Submit aux command * @dp: DisplayPort IP core structure * @cmd: aux command * @addr: aux address * @buf: buffer for command data * @bytes: number of bytes for @buf * @reply: reply code to be returned * * Submit an aux command. All aux related commands, native or i2c aux * read/write, are submitted through this function. The function is mapped to * the transfer function of struct drm_dp_aux. This function involves in * multiple register reads/writes, thus synchronization is needed, and it is * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep * if there's no immediate reply to the command submission. The reply code is * returned at @reply if @reply != NULL. * * Return: 0 if the command is submitted properly, or corresponding error code: * -EBUSY when there is any request already being processed * -ETIMEDOUT when receiving reply is timed out * -EIO when received bytes are less than requested */ static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, u8 *buf, u8 bytes, u8 *reply) { … } static ssize_t zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { … } /** * zynqmp_dp_aux_init - Initialize and register the DP AUX * @dp: DisplayPort IP core structure * * Program the AUX clock divider and filter and register the DP AUX adapter. * * Return: 0 on success, error value otherwise */ static int zynqmp_dp_aux_init(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_aux_cleanup - Cleanup the DP AUX * @dp: DisplayPort IP core structure * * Unregister the DP AUX adapter. */ static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp) { … } /* ----------------------------------------------------------------------------- * DisplayPort Generic Support */ /** * zynqmp_dp_update_misc - Write the misc registers * @dp: DisplayPort IP core structure * * The misc register values are stored in the structure, and this * function applies the values into the registers. */ static void zynqmp_dp_update_misc(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_set_format - Set the input format * @dp: DisplayPort IP core structure * @info: Display info * @format: input format * @bpc: bits per component * * Update misc register values based on input @format and @bpc. * * Return: 0 on success, or -EINVAL. */ static int zynqmp_dp_set_format(struct zynqmp_dp *dp, const struct drm_display_info *info, enum zynqmp_dpsub_format format, unsigned int bpc) { … } /** * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values * @dp: DisplayPort IP core structure * @mode: requested display mode * * Set the transfer unit, and calculate all transfer unit size related values. * Calculation is based on DP and IP core specification. */ static void zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, const struct drm_display_mode *mode) { … } /** * zynqmp_dp_encoder_mode_set_stream - Configure the main stream * @dp: DisplayPort IP core structure * @mode: requested display mode * * Configure the main stream based on the requested mode @mode. Calculation is * based on IP core specification. */ static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, const struct drm_display_mode *mode) { … } /* ----------------------------------------------------------------------------- * DISP Configuration */ /** * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer * @dp: DisplayPort IP core structure * * Return: The first connected live display layer or NULL if none of the live * layers are connected. */ static struct zynqmp_disp_layer * zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp) { … } static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, struct drm_bridge_state *old_bridge_state) { … } static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp, struct drm_bridge_state *old_bridge_state) { … } /* ----------------------------------------------------------------------------- * DRM Bridge */ static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { … } static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge) { … } static enum drm_mode_status zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { … } static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { … } static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { … } #define ZYNQMP_DP_MIN_H_BACKPORCH … static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { … } static enum drm_connector_status zynqmp_dp_bridge_detect(struct drm_bridge *bridge) { … } static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) { … } static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts) { … } static u32 * zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state, u32 output_fmt, unsigned int *num_input_fmts) { … } static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = …; /* ----------------------------------------------------------------------------- * Interrupt Handling */ /** * zynqmp_dp_enable_vblank - Enable vblank * @dp: DisplayPort IP core structure * * Enable vblank interrupt */ void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp) { … } /** * zynqmp_dp_disable_vblank - Disable vblank * @dp: DisplayPort IP core structure * * Disable vblank interrupt */ void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp) { … } static void zynqmp_dp_hpd_work_func(struct work_struct *work) { … } static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data) { … } /* ----------------------------------------------------------------------------- * Initialization & Cleanup */ int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub) { … } void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub) { … }
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