linux/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * ZynqMP Display Controller Driver - Register Definitions
 *
 * Copyright (C) 2017 - 2020 Xilinx, Inc.
 *
 * Authors:
 * - Hyun Woo Kwon <[email protected]>
 * - Laurent Pinchart <[email protected]>
 */

#ifndef _ZYNQMP_DISP_REGS_H_
#define _ZYNQMP_DISP_REGS_H_

#include <linux/bits.h>

/* Blender registers */
#define ZYNQMP_DISP_V_BLEND_BG_CLR_0
#define ZYNQMP_DISP_V_BLEND_BG_CLR_1
#define ZYNQMP_DISP_V_BLEND_BG_CLR_2
#define ZYNQMP_DISP_V_BLEND_BG_MAX
#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA
#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(n)
#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(n)
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS
#define ZYNQMP_DISP_V_BLEND_NUM_COEFF
#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET
#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(n)
#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(n)
#define ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(n)
#define ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(n)
#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(n)
#define ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(n)
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3

/* AV buffer manager registers */
#define ZYNQMP_DISP_AV_BUF_FMT
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP
#define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY
#define ZYNQMP_DISP_AV_BUF_CHBUF(n)
#define ZYNQMP_DISP_AV_BUF_CHBUF_EN
#define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX
#define ZYNQMP_DISP_AV_BUF_STATUS
#define ZYNQMP_DISP_AV_BUF_STC_CTRL
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_SHIFT
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VSYNC
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VID
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_AUD
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_INT_VSYNC
#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE0
#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE1
#define ZYNQMP_DISP_AV_BUF_STC_ADJ
#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS0
#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS1
#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS0
#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS1
#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS0
#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS1
#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS0
#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS1
#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT0
#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT1
#define ZYNQMP_DISP_AV_BUF_OUTPUT
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE
#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE
#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN
#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0
#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1
#define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT
#define ZYNQMP_DISP_AV_BUF_CLK_SRC
#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS
#define ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS
#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING
#define ZYNQMP_DISP_AV_BUF_SRST_REG
#define ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST
#define ZYNQMP_DISP_AV_BUF_AUDIO_CH_CONFIG
#define ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(n)
#define ZYNQMP_DISP_AV_BUF_VID_COMP_SF(n)
#define ZYNQMP_DISP_AV_BUF_LIVD_VID_COMP_SF(n)
#define ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG
#define ZYNQMP_DISP_AV_BUF_LIVD_GFX_COMP_SF(n)
#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG
#define ZYNQMP_DISP_AV_BUF_4BIT_SF
#define ZYNQMP_DISP_AV_BUF_5BIT_SF
#define ZYNQMP_DISP_AV_BUF_6BIT_SF
#define ZYNQMP_DISP_AV_BUF_8BIT_SF
#define ZYNQMP_DISP_AV_BUF_10BIT_SF
#define ZYNQMP_DISP_AV_BUF_NULL_SF
#define ZYNQMP_DISP_AV_BUF_NUM_SF
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK
#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST
#define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY

/* Audio registers */
#define ZYNQMP_DISP_AUD_MIXER_VOLUME
#define ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE
#define ZYNQMP_DISP_AUD_MIXER_META_DATA
#define ZYNQMP_DISP_AUD_CH_STATUS0
#define ZYNQMP_DISP_AUD_CH_STATUS1
#define ZYNQMP_DISP_AUD_CH_STATUS2
#define ZYNQMP_DISP_AUD_CH_STATUS3
#define ZYNQMP_DISP_AUD_CH_STATUS4
#define ZYNQMP_DISP_AUD_CH_STATUS5
#define ZYNQMP_DISP_AUD_CH_A_DATA0
#define ZYNQMP_DISP_AUD_CH_A_DATA1
#define ZYNQMP_DISP_AUD_CH_A_DATA2
#define ZYNQMP_DISP_AUD_CH_A_DATA3
#define ZYNQMP_DISP_AUD_CH_A_DATA4
#define ZYNQMP_DISP_AUD_CH_A_DATA5
#define ZYNQMP_DISP_AUD_CH_B_DATA0
#define ZYNQMP_DISP_AUD_CH_B_DATA1
#define ZYNQMP_DISP_AUD_CH_B_DATA2
#define ZYNQMP_DISP_AUD_CH_B_DATA3
#define ZYNQMP_DISP_AUD_CH_B_DATA4
#define ZYNQMP_DISP_AUD_CH_B_DATA5
#define ZYNQMP_DISP_AUD_SOFT_RESET
#define ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST

#endif /* _ZYNQMP_DISP_REGS_H_ */