/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2010 Sascha Hauer <[email protected]> * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. */ #ifndef __IPU_PRV_H__ #define __IPU_PRV_H__ struct ipu_soc; #include <linux/io.h> #include <linux/types.h> #include <linux/device.h> #include <linux/clk.h> #include <linux/platform_device.h> #include <video/imx-ipu-v3.h> #define IPU_MCU_T_DEFAULT … #define IPU_CM_IDMAC_REG_OFS … #define IPU_CM_IC_REG_OFS … #define IPU_CM_IRT_REG_OFS … #define IPU_CM_CSI0_REG_OFS … #define IPU_CM_CSI1_REG_OFS … #define IPU_CM_SMFC_REG_OFS … #define IPU_CM_DC_REG_OFS … #define IPU_CM_DMFC_REG_OFS … /* Register addresses */ /* IPU Common registers */ #define IPU_CM_REG(offset) … #define IPU_CONF … #define IPU_SRM_PRI1 … #define IPU_SRM_PRI2 … #define IPU_FS_PROC_FLOW1 … #define IPU_FS_PROC_FLOW2 … #define IPU_FS_PROC_FLOW3 … #define IPU_FS_DISP_FLOW1 … #define IPU_FS_DISP_FLOW2 … #define IPU_SKIP … #define IPU_DISP_ALT_CONF … #define IPU_DISP_GEN … #define IPU_DISP_ALT1 … #define IPU_DISP_ALT2 … #define IPU_DISP_ALT3 … #define IPU_DISP_ALT4 … #define IPU_SNOOP … #define IPU_MEM_RST … #define IPU_PM … #define IPU_GPR … #define IPU_CHA_DB_MODE_SEL(ch) … #define IPU_ALT_CHA_DB_MODE_SEL(ch) … #define IPU_CHA_CUR_BUF(ch) … #define IPU_ALT_CUR_BUF0 … #define IPU_ALT_CUR_BUF1 … #define IPU_SRM_STAT … #define IPU_PROC_TASK_STAT … #define IPU_DISP_TASK_STAT … #define IPU_CHA_BUF0_RDY(ch) … #define IPU_CHA_BUF1_RDY(ch) … #define IPU_CHA_BUF2_RDY(ch) … #define IPU_ALT_CHA_BUF0_RDY(ch) … #define IPU_ALT_CHA_BUF1_RDY(ch) … #define IPU_INT_CTRL(n) … #define IPU_INT_STAT(n) … /* SRM_PRI2 */ #define DP_S_SRM_MODE_MASK … #define DP_S_SRM_MODE_NOW … #define DP_S_SRM_MODE_NEXT_FRAME … /* FS_PROC_FLOW1 */ #define FS_PRPENC_ROT_SRC_SEL_MASK … #define FS_PRPENC_ROT_SRC_SEL_ENC … #define FS_PRPVF_ROT_SRC_SEL_MASK … #define FS_PRPVF_ROT_SRC_SEL_VF … #define FS_PP_SRC_SEL_MASK … #define FS_PP_ROT_SRC_SEL_MASK … #define FS_PP_ROT_SRC_SEL_PP … #define FS_VDI1_SRC_SEL_MASK … #define FS_VDI3_SRC_SEL_MASK … #define FS_PRP_SRC_SEL_MASK … #define FS_VDI_SRC_SEL_MASK … #define FS_VDI_SRC_SEL_CSI_DIRECT … #define FS_VDI_SRC_SEL_VDOA … /* FS_PROC_FLOW2 */ #define FS_PRP_ENC_DEST_SEL_MASK … #define FS_PRP_ENC_DEST_SEL_IRT_ENC … #define FS_PRPVF_DEST_SEL_MASK … #define FS_PRPVF_DEST_SEL_IRT_VF … #define FS_PRPVF_ROT_DEST_SEL_MASK … #define FS_PP_DEST_SEL_MASK … #define FS_PP_DEST_SEL_IRT_PP … #define FS_PP_ROT_DEST_SEL_MASK … #define FS_PRPENC_ROT_DEST_SEL_MASK … #define FS_PRP_DEST_SEL_MASK … #define IPU_DI0_COUNTER_RELEASE … #define IPU_DI1_COUNTER_RELEASE … #define IPU_IDMAC_REG(offset) … #define IDMAC_CONF … #define IDMAC_CHA_EN(ch) … #define IDMAC_SEP_ALPHA … #define IDMAC_ALT_SEP_ALPHA … #define IDMAC_CHA_PRI(ch) … #define IDMAC_WM_EN(ch) … #define IDMAC_CH_LOCK_EN_1 … #define IDMAC_CH_LOCK_EN_2 … #define IDMAC_SUB_ADDR_0 … #define IDMAC_SUB_ADDR_1 … #define IDMAC_SUB_ADDR_2 … #define IDMAC_BAND_EN(ch) … #define IDMAC_CHA_BUSY(ch) … #define IPU_NUM_IRQS … enum ipu_modules { … }; struct ipuv3_channel { … }; struct ipu_cpmem; struct ipu_csi; struct ipu_dc_priv; struct ipu_dmfc_priv; struct ipu_di; struct ipu_ic_priv; struct ipu_vdi; struct ipu_image_convert_priv; struct ipu_smfc_priv; struct ipu_pre; struct ipu_prg; struct ipu_devtype; struct ipu_soc { … }; static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset) { … } static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value, unsigned offset) { … } void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync); int ipu_module_enable(struct ipu_soc *ipu, u32 mask); int ipu_module_disable(struct ipu_soc *ipu, u32 mask); bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno); int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id, unsigned long base, u32 module, struct clk *clk_ipu); void ipu_csi_exit(struct ipu_soc *ipu, int id); int ipu_ic_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, unsigned long tpmem_base); void ipu_ic_exit(struct ipu_soc *ipu); int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, u32 module); void ipu_vdi_exit(struct ipu_soc *ipu); int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev); void ipu_image_convert_exit(struct ipu_soc *ipu); int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, unsigned long base, u32 module, struct clk *ipu_clk); void ipu_di_exit(struct ipu_soc *ipu, int id); int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, struct clk *ipu_clk); void ipu_dmfc_exit(struct ipu_soc *ipu); int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); void ipu_dp_exit(struct ipu_soc *ipu); int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, unsigned long template_base); void ipu_dc_exit(struct ipu_soc *ipu); int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); void ipu_cpmem_exit(struct ipu_soc *ipu); int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); void ipu_smfc_exit(struct ipu_soc *ipu); struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index); int ipu_pre_get_available_count(void); int ipu_pre_get(struct ipu_pre *pre); void ipu_pre_put(struct ipu_pre *pre); u32 ipu_pre_get_baddr(struct ipu_pre *pre); void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, unsigned int height, unsigned int stride, u32 format, uint64_t modifier, unsigned int bufaddr); void ipu_pre_update(struct ipu_pre *pre, uint64_t modifier, unsigned int bufaddr); bool ipu_pre_update_pending(struct ipu_pre *pre); struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id); extern struct platform_driver ipu_pre_drv; extern struct platform_driver ipu_prg_drv; #endif /* __IPU_PRV_H__ */
Codebase Browser
linux