linux/drivers/gpu/ipu-v3/ipu-di.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2010 Sascha Hauer <[email protected]>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 */
#include <linux/export.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>

#include <video/imx-ipu-v3.h>
#include "ipu-prv.h"

struct ipu_di {};

static DEFINE_MUTEX(di_mutex);

struct di_sync_config {};

enum di_pins {};

enum di_sync_wave {};

#define SYNC_WAVE

#define DI_GENERAL
#define DI_BS_CLKGEN0
#define DI_BS_CLKGEN1
#define DI_SW_GEN0(gen)
#define DI_SW_GEN1(gen)
#define DI_STP_REP(gen)
#define DI_SYNC_AS_GEN
#define DI_DW_GEN(gen)
#define DI_DW_SET(gen, set)
#define DI_SER_CONF
#define DI_SSC
#define DI_POL
#define DI_AW0
#define DI_AW1
#define DI_SCR_CONF
#define DI_STAT

#define DI_SW_GEN0_RUN_COUNT(x)
#define DI_SW_GEN0_RUN_SRC(x)
#define DI_SW_GEN0_OFFSET_COUNT(x)
#define DI_SW_GEN0_OFFSET_SRC(x)

#define DI_SW_GEN1_CNT_POL_GEN_EN(x)
#define DI_SW_GEN1_CNT_CLR_SRC(x)
#define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x)
#define DI_SW_GEN1_CNT_POL_CLR_SRC(x)
#define DI_SW_GEN1_CNT_DOWN(x)
#define DI_SW_GEN1_CNT_UP(x)
#define DI_SW_GEN1_AUTO_RELOAD

#define DI_DW_GEN_ACCESS_SIZE_OFFSET
#define DI_DW_GEN_COMPONENT_SIZE_OFFSET

#define DI_GEN_POLARITY_1
#define DI_GEN_POLARITY_2
#define DI_GEN_POLARITY_3
#define DI_GEN_POLARITY_4
#define DI_GEN_POLARITY_5
#define DI_GEN_POLARITY_6
#define DI_GEN_POLARITY_7
#define DI_GEN_POLARITY_8
#define DI_GEN_POLARITY_DISP_CLK
#define DI_GEN_DI_CLK_EXT
#define DI_GEN_DI_VSYNC_EXT

#define DI_POL_DRDY_DATA_POLARITY
#define DI_POL_DRDY_POLARITY_15

#define DI_VSYNC_SEL_OFFSET

static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset)
{}

static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset)
{}

static void ipu_di_data_wave_config(struct ipu_di *di,
				     int wave_gen,
				     int access_size, int component_size)
{}

static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin,
		int set, int up, int down)
{}

static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
		int start, int count)
{}

static void ipu_di_sync_config_interlaced(struct ipu_di *di,
		struct ipu_di_signal_cfg *sig)
{}

static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
		struct ipu_di_signal_cfg *sig, int div)
{}

static void ipu_di_config_clock(struct ipu_di *di,
	const struct ipu_di_signal_cfg *sig)
{}

/*
 * This function is called to adjust a video mode to IPU restrictions.
 * It is meant to be called from drm crtc mode_fixup() methods.
 */
int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode)
{}
EXPORT_SYMBOL_GPL();

static u32 ipu_di_gen_polarity(int pin)
{}

int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
{}
EXPORT_SYMBOL_GPL();

int ipu_di_enable(struct ipu_di *di)
{}
EXPORT_SYMBOL_GPL();

int ipu_di_disable(struct ipu_di *di)
{}
EXPORT_SYMBOL_GPL();

int ipu_di_get_num(struct ipu_di *di)
{}
EXPORT_SYMBOL_GPL();

static DEFINE_MUTEX(ipu_di_lock);

struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp)
{}
EXPORT_SYMBOL_GPL();

void ipu_di_put(struct ipu_di *di)
{}
EXPORT_SYMBOL_GPL();

int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
		unsigned long base,
		u32 module, struct clk *clk_ipu)
{}

void ipu_di_exit(struct ipu_soc *ipu, int id)
{}