// SPDX-License-Identifier: GPL-2.0 // // Register map access API - SPI AVMM support // // Copyright (C) 2018-2020 Intel Corporation. All rights reserved. #include <linux/module.h> #include <linux/regmap.h> #include <linux/spi/spi.h> #include <linux/swab.h> /* * This driver implements the regmap operations for a generic SPI * master to access the registers of the spi slave chip which has an * Avalone bus in it. * * The "SPI slave to Avalon Master Bridge" (spi-avmm) IP should be integrated * in the spi slave chip. The IP acts as a bridge to convert encoded streams of * bytes from the host to the internal register read/write on Avalon bus. In * order to issue register access requests to the slave chip, the host should * send formatted bytes that conform to the transfer protocol. * The transfer protocol contains 3 layers: transaction layer, packet layer * and physical layer. * * Reference Documents could be found at: * https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html * * Chapter "SPI Slave/JTAG to Avalon Master Bridge Cores" is a general * introduction to the protocol. * * Chapter "Avalon Packets to Transactions Converter Core" describes * the transaction layer. * * Chapter "Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores" * describes the packet layer. * * Chapter "Avalon-ST Serial Peripheral Interface Core" describes the * physical layer. * * * When host issues a regmap read/write, the driver will transform the request * to byte stream layer by layer. It formats the register addr, value and * length to the transaction layer request, then converts the request to packet * layer bytes stream and then to physical layer bytes stream. Finally the * driver sends the formatted byte stream over SPI bus to the slave chip. * * The spi-avmm IP on the slave chip decodes the byte stream and initiates * register read/write on its internal Avalon bus, and then encodes the * response to byte stream and sends back to host. * * The driver receives the byte stream, reverses the 3 layers transformation, * and finally gets the response value (read out data for register read, * successful written size for register write). */ #define PKT_SOP … #define PKT_EOP … #define PKT_CHANNEL … #define PKT_ESC … #define PHY_IDLE … #define PHY_ESC … #define TRANS_CODE_WRITE … #define TRANS_CODE_SEQ_WRITE … #define TRANS_CODE_READ … #define TRANS_CODE_SEQ_READ … #define TRANS_CODE_NO_TRANS … #define SPI_AVMM_XFER_TIMEOUT … /* slave's register addr is 32 bits */ #define SPI_AVMM_REG_SIZE … /* slave's register value is 32 bits */ #define SPI_AVMM_VAL_SIZE … /* * max rx size could be larger. But considering the buffer consuming, * it is proper that we limit 1KB xfer at max. */ #define MAX_READ_CNT … #define MAX_WRITE_CNT … struct trans_req_header { … } __packed; struct trans_resp_header { … } __packed; #define TRANS_REQ_HD_SIZE … #define TRANS_RESP_HD_SIZE … /* * In transaction layer, * the write request format is: Transaction request header + data * the read request format is: Transaction request header * the write response format is: Transaction response header * the read response format is: pure data, no Transaction response header */ #define TRANS_WR_TX_SIZE(n) … #define TRANS_RD_TX_SIZE … #define TRANS_TX_MAX … #define TRANS_RD_RX_SIZE(n) … #define TRANS_WR_RX_SIZE … #define TRANS_RX_MAX … /* tx & rx share one transaction layer buffer */ #define TRANS_BUF_SIZE … /* * In tx phase, the host prepares all the phy layer bytes of a request in the * phy buffer and sends them in a batch. * * The packet layer and physical layer defines several special chars for * various purpose, when a transaction layer byte hits one of these special * chars, it should be escaped. The escape rule is, "Escape char first, * following the byte XOR'ed with 0x20". * * This macro defines the max possible length of the phy data. In the worst * case, all transaction layer bytes need to be escaped (so the data length * doubles), plus 4 special chars (SOP, CHANNEL, CHANNEL_NUM, EOP). Finally * we should make sure the length is aligned to SPI BPW. */ #define PHY_TX_MAX … /* * Unlike tx, phy rx is affected by possible PHY_IDLE bytes from slave, the max * length of the rx bit stream is unpredictable. So the driver reads the words * one by one, and parses each word immediately into transaction layer buffer. * Only one word length of phy buffer is used for rx. */ #define PHY_BUF_SIZE … /** * struct spi_avmm_bridge - SPI slave to AVMM bus master bridge * * @spi: spi slave associated with this bridge. * @word_len: bytes of word for spi transfer. * @trans_len: length of valid data in trans_buf. * @phy_len: length of valid data in phy_buf. * @trans_buf: the bridge buffer for transaction layer data. * @phy_buf: the bridge buffer for physical layer data. * @swap_words: the word swapping cb for phy data. NULL if not needed. * * As a device's registers are implemented on the AVMM bus address space, it * requires the driver to issue formatted requests to spi slave to AVMM bus * master bridge to perform register access. */ struct spi_avmm_bridge { … }; static void br_swap_words_32(void *buf, unsigned int len) { … } /* * Format transaction layer data in br->trans_buf according to the register * access request, Store valid transaction layer data length in br->trans_len. */ static int br_trans_tx_prepare(struct spi_avmm_bridge *br, bool is_read, u32 reg, u32 *wr_val, u32 count) { … } /* * Convert transaction layer data (in br->trans_buf) to phy layer data, store * them in br->phy_buf. Pad the phy_buf aligned with SPI's BPW. Store valid phy * layer data length in br->phy_len. * * phy_buf len should be aligned with SPI's BPW. Spare bytes should be padded * with PHY_IDLE, then the slave will just drop them. * * The driver will not simply pad 4a at the tail. The concern is that driver * will not store MISO data during tx phase, if the driver pads 4a at the tail, * it is possible that if the slave is fast enough to response at the padding * time. As a result these rx bytes are lost. In the following case, 7a,7c,00 * will lost. * MOSI ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|4a|4a|4a| |XX|XX|... * MISO ...|4a|4a|4a|4a| |4a|4a|4a|4a| |4a|4a|4a|4a| |4a|7a|7c|00| |78|56|... * * So the driver moves EOP and bytes after EOP to the end of the aligned size, * then fill the hole with PHY_IDLE. As following: * before pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40| * after pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|4a| |4a|4a|7b|40| * Then if the slave will not get the entire packet before the tx phase is * over, it can't responsed to anything either. */ static int br_pkt_phy_tx_prepare(struct spi_avmm_bridge *br) { … } /* * In tx phase, the slave only returns PHY_IDLE (0x4a). So the driver will * ignore rx in tx phase. */ static int br_do_tx(struct spi_avmm_bridge *br) { … } /* * This function read the rx byte stream from SPI word by word and convert * them to transaction layer data in br->trans_buf. It also stores the length * of rx transaction layer data in br->trans_len * * The slave may send an unknown number of PHY_IDLEs in rx phase, so we cannot * prepare a fixed length buffer to receive all of the rx data in a batch. We * have to read word by word and convert them to transaction layer data at * once. */ static int br_do_rx_and_pkt_phy_parse(struct spi_avmm_bridge *br) { … } /* * For read transactions, the avmm bus will directly return register values * without transaction response header. */ static int br_rd_trans_rx_parse(struct spi_avmm_bridge *br, u32 *val, unsigned int expected_count) { … } /* * For write transactions, the slave will return a transaction response * header. */ static int br_wr_trans_rx_parse(struct spi_avmm_bridge *br, unsigned int expected_count) { … } static int do_reg_access(void *context, bool is_read, unsigned int reg, unsigned int *value, unsigned int count) { … } static int regmap_spi_avmm_gather_write(void *context, const void *reg_buf, size_t reg_len, const void *val_buf, size_t val_len) { … } static int regmap_spi_avmm_write(void *context, const void *data, size_t bytes) { … } static int regmap_spi_avmm_read(void *context, const void *reg_buf, size_t reg_len, void *val_buf, size_t val_len) { … } static struct spi_avmm_bridge * spi_avmm_bridge_ctx_gen(struct spi_device *spi) { … } static void spi_avmm_bridge_ctx_free(void *context) { … } static const struct regmap_bus regmap_spi_avmm_bus = …; struct regmap *__regmap_init_spi_avmm(struct spi_device *spi, const struct regmap_config *config, struct lock_class_key *lock_key, const char *lock_name) { … } EXPORT_SYMBOL_GPL(…); struct regmap *__devm_regmap_init_spi_avmm(struct spi_device *spi, const struct regmap_config *config, struct lock_class_key *lock_key, const char *lock_name) { … } EXPORT_SYMBOL_GPL(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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