/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ #ifndef _MEI_HW_MEI_REGS_H_ #define _MEI_HW_MEI_REGS_H_ /* * MEI device IDs */ #define MEI_DEV_ID_82946GZ … #define MEI_DEV_ID_82G35 … #define MEI_DEV_ID_82Q965 … #define MEI_DEV_ID_82G965 … #define MEI_DEV_ID_82GM965 … #define MEI_DEV_ID_82GME965 … #define MEI_DEV_ID_ICH9_82Q35 … #define MEI_DEV_ID_ICH9_82G33 … #define MEI_DEV_ID_ICH9_82Q33 … #define MEI_DEV_ID_ICH9_82X38 … #define MEI_DEV_ID_ICH9_3200 … #define MEI_DEV_ID_ICH9_6 … #define MEI_DEV_ID_ICH9_7 … #define MEI_DEV_ID_ICH9_8 … #define MEI_DEV_ID_ICH9_9 … #define MEI_DEV_ID_ICH9_10 … #define MEI_DEV_ID_ICH9M_1 … #define MEI_DEV_ID_ICH9M_2 … #define MEI_DEV_ID_ICH9M_3 … #define MEI_DEV_ID_ICH9M_4 … #define MEI_DEV_ID_ICH10_1 … #define MEI_DEV_ID_ICH10_2 … #define MEI_DEV_ID_ICH10_3 … #define MEI_DEV_ID_ICH10_4 … #define MEI_DEV_ID_IBXPK_1 … #define MEI_DEV_ID_IBXPK_2 … #define MEI_DEV_ID_CPT_1 … #define MEI_DEV_ID_PBG_1 … #define MEI_DEV_ID_PPT_1 … #define MEI_DEV_ID_PPT_2 … #define MEI_DEV_ID_PPT_3 … #define MEI_DEV_ID_LPT_H … #define MEI_DEV_ID_LPT_W … #define MEI_DEV_ID_LPT_LP … #define MEI_DEV_ID_LPT_HR … #define MEI_DEV_ID_WPT_LP … #define MEI_DEV_ID_WPT_LP_2 … #define MEI_DEV_ID_SPT … #define MEI_DEV_ID_SPT_2 … #define MEI_DEV_ID_SPT_3 … #define MEI_DEV_ID_SPT_H … #define MEI_DEV_ID_SPT_H_2 … #define MEI_DEV_ID_LBG … #define MEI_DEV_ID_BXT_M … #define MEI_DEV_ID_APL_I … #define MEI_DEV_ID_DNV_IE … #define MEI_DEV_ID_GLK … #define MEI_DEV_ID_KBP … #define MEI_DEV_ID_KBP_2 … #define MEI_DEV_ID_KBP_3 … #define MEI_DEV_ID_CNP_LP … #define MEI_DEV_ID_CNP_LP_3 … #define MEI_DEV_ID_CNP_H … #define MEI_DEV_ID_CNP_H_3 … #define MEI_DEV_ID_CMP_LP … #define MEI_DEV_ID_CMP_LP_3 … #define MEI_DEV_ID_CMP_V … #define MEI_DEV_ID_CMP_H … #define MEI_DEV_ID_CMP_H_3 … #define MEI_DEV_ID_CDF … #define MEI_DEV_ID_ICP_LP … #define MEI_DEV_ID_ICP_N … #define MEI_DEV_ID_JSP_N … #define MEI_DEV_ID_TGP_LP … #define MEI_DEV_ID_TGP_H … #define MEI_DEV_ID_MCC … #define MEI_DEV_ID_MCC_4 … #define MEI_DEV_ID_EBG … #define MEI_DEV_ID_ADP_S … #define MEI_DEV_ID_ADP_LP … #define MEI_DEV_ID_ADP_P … #define MEI_DEV_ID_ADP_N … #define MEI_DEV_ID_RPL_S … #define MEI_DEV_ID_MTL_M … #define MEI_DEV_ID_ARL_S … #define MEI_DEV_ID_ARL_H … #define MEI_DEV_ID_LNL_M … /* * MEI HW Section */ /* Host Firmware Status Registers in PCI Config Space */ #define PCI_CFG_HFS_1 … #define PCI_CFG_HFS_1_D0I3_MSK … #define PCI_CFG_HFS_1_OPMODE_MSK … #define PCI_CFG_HFS_1_OPMODE_SPS … #define PCI_CFG_HFS_2 … #define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR … #define PCI_CFG_HFS_2_PM_CM_RESET_ERROR … #define PCI_CFG_HFS_2_PM_EVENT_MASK … #define PCI_CFG_HFS_3 … #define PCI_CFG_HFS_3_FW_SKU_MSK … #define PCI_CFG_HFS_3_FW_SKU_IGN … #define PCI_CFG_HFS_3_FW_SKU_SPS … #define PCI_CFG_HFS_4 … #define PCI_CFG_HFS_5 … #define GSC_CFG_HFS_5_BOOT_TYPE_MSK … #define GSC_CFG_HFS_5_BOOT_TYPE_PXP … #define PCI_CFG_HFS_6 … /* MEI registers */ /* H_CB_WW - Host Circular Buffer (CB) Write Window register */ #define H_CB_WW … /* H_CSR - Host Control Status register */ #define H_CSR … /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */ #define ME_CB_RW … /* ME_CSR_HA - ME Control Status Host Access register (read only) */ #define ME_CSR_HA … /* H_HGC_CSR - PGI register */ #define H_HPG_CSR … /* H_D0I3C - D0I3 Control */ #define H_D0I3C … #define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG … #define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG … #define H_GSC_EXT_OP_MEM_LIMIT_REG … #define GSC_EXT_OP_MEM_VALID … /* register bits of H_CSR (Host Control Status register) */ /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ #define H_CBD … /* Host Circular Buffer Write Pointer */ #define H_CBWP … /* Host Circular Buffer Read Pointer */ #define H_CBRP … /* Host Reset */ #define H_RST … /* Host Ready */ #define H_RDY … /* Host Interrupt Generate */ #define H_IG … /* Host Interrupt Status */ #define H_IS … /* Host Interrupt Enable */ #define H_IE … /* Host D0I3 Interrupt Enable */ #define H_D0I3C_IE … /* Host D0I3 Interrupt Status */ #define H_D0I3C_IS … /* H_CSR masks */ #define H_CSR_IE_MASK … #define H_CSR_IS_MASK … /* register bits of ME_CSR_HA (ME Control Status Host Access register) */ /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only access to ME_CBD */ #define ME_CBD_HRA … /* ME CB Write Pointer HRA - host read only access to ME_CBWP */ #define ME_CBWP_HRA … /* ME CB Read Pointer HRA - host read only access to ME_CBRP */ #define ME_CBRP_HRA … /* ME Power Gate Isolation Capability HRA - host ready only access */ #define ME_PGIC_HRA … /* ME Reset HRA - host read only access to ME_RST */ #define ME_RST_HRA … /* ME Ready HRA - host read only access to ME_RDY */ #define ME_RDY_HRA … /* ME Interrupt Generate HRA - host read only access to ME_IG */ #define ME_IG_HRA … /* ME Interrupt Status HRA - host read only access to ME_IS */ #define ME_IS_HRA … /* ME Interrupt Enable HRA - host read only access to ME_IE */ #define ME_IE_HRA … /* TRC control shadow register */ #define ME_TRC … /* H_HPG_CSR register bits */ #define H_HPG_CSR_PGIHEXR … #define H_HPG_CSR_PGI … /* H_D0I3C register bits */ #define H_D0I3C_CIP … #define H_D0I3C_IR … #define H_D0I3C_I3 … #define H_D0I3C_RR … #endif /* _MEI_HW_MEI_REGS_H_ */
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