// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ #include <linux/pci.h> #include <linux/kthread.h> #include <linux/interrupt.h> #include <linux/pm_runtime.h> #include <linux/sizes.h> #include <linux/delay.h> #include "mei_dev.h" #include "hbm.h" #include "hw-me.h" #include "hw-me-regs.h" #include "mei-trace.h" /** * mei_me_reg_read - Reads 32bit data from the mei device * * @hw: the me hardware structure * @offset: offset from which to read the data * * Return: register value (u32) */ static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, unsigned long offset) { … } /** * mei_me_reg_write - Writes 32bit data to the mei device * * @hw: the me hardware structure * @offset: offset from which to write the data * @value: register value to write (u32) */ static inline void mei_me_reg_write(const struct mei_me_hw *hw, unsigned long offset, u32 value) { … } /** * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer * read window register * * @dev: the device structure * * Return: ME_CB_RW register value (u32) */ static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) { … } /** * mei_me_hcbww_write - write 32bit data to the host circular buffer * * @dev: the device structure * @data: 32bit data to be written to the host circular buffer */ static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) { … } /** * mei_me_mecsr_read - Reads 32bit data from the ME CSR * * @dev: the device structure * * Return: ME_CSR_HA register value (u32) */ static inline u32 mei_me_mecsr_read(const struct mei_device *dev) { … } /** * mei_hcsr_read - Reads 32bit data from the host CSR * * @dev: the device structure * * Return: H_CSR register value (u32) */ static inline u32 mei_hcsr_read(const struct mei_device *dev) { … } /** * mei_hcsr_write - writes H_CSR register to the mei device * * @dev: the device structure * @reg: new register value */ static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) { … } /** * mei_hcsr_set - writes H_CSR register to the mei device, * and ignores the H_IS bit for it is write-one-to-zero. * * @dev: the device structure * @reg: new register value */ static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) { … } /** * mei_hcsr_set_hig - set host interrupt (set H_IG) * * @dev: the device structure */ static inline void mei_hcsr_set_hig(struct mei_device *dev) { … } /** * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register * * @dev: the device structure * * Return: H_D0I3C register value (u32) */ static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) { … } /** * mei_me_d0i3c_write - writes H_D0I3C register to device * * @dev: the device structure * @reg: new register value */ static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) { … } /** * mei_me_trc_status - read trc status register * * @dev: mei device * @trc: trc status register value * * Return: 0 on success, error otherwise */ static int mei_me_trc_status(struct mei_device *dev, u32 *trc) { … } /** * mei_me_fw_status - read fw status register from pci config space * * @dev: mei device * @fw_status: fw status register values * * Return: 0 on success, error otherwise */ static int mei_me_fw_status(struct mei_device *dev, struct mei_fw_status *fw_status) { … } /** * mei_me_hw_config - configure hw dependent settings * * @dev: mei device * * Return: * * -EINVAL when read_fws is not set * * 0 on success * */ static int mei_me_hw_config(struct mei_device *dev) { … } /** * mei_me_pg_state - translate internal pg state * to the mei power gating state * * @dev: mei device * * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise */ static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) { … } static inline u32 me_intr_src(u32 hcsr) { … } /** * me_intr_disable - disables mei device interrupts * using supplied hcsr register value. * * @dev: the device structure * @hcsr: supplied hcsr register value */ static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) { … } /** * me_intr_clear - clear and stop interrupts * * @dev: the device structure * @hcsr: supplied hcsr register value */ static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) { … } /** * mei_me_intr_clear - clear and stop interrupts * * @dev: the device structure */ static void mei_me_intr_clear(struct mei_device *dev) { … } /** * mei_me_intr_enable - enables mei device interrupts * * @dev: the device structure */ static void mei_me_intr_enable(struct mei_device *dev) { … } /** * mei_me_intr_disable - disables mei device interrupts * * @dev: the device structure */ static void mei_me_intr_disable(struct mei_device *dev) { … } /** * mei_me_synchronize_irq - wait for pending IRQ handlers * * @dev: the device structure */ static void mei_me_synchronize_irq(struct mei_device *dev) { … } /** * mei_me_hw_reset_release - release device from the reset * * @dev: the device structure */ static void mei_me_hw_reset_release(struct mei_device *dev) { … } /** * mei_me_host_set_ready - enable device * * @dev: mei device */ static void mei_me_host_set_ready(struct mei_device *dev) { … } /** * mei_me_host_is_ready - check whether the host has turned ready * * @dev: mei device * Return: bool */ static bool mei_me_host_is_ready(struct mei_device *dev) { … } /** * mei_me_hw_is_ready - check whether the me(hw) has turned ready * * @dev: mei device * Return: bool */ static bool mei_me_hw_is_ready(struct mei_device *dev) { … } /** * mei_me_hw_is_resetting - check whether the me(hw) is in reset * * @dev: mei device * Return: bool */ static bool mei_me_hw_is_resetting(struct mei_device *dev) { … } /** * mei_gsc_pxp_check - check for gsc firmware entering pxp mode * * @dev: the device structure */ static void mei_gsc_pxp_check(struct mei_device *dev) { … } /** * mei_me_hw_ready_wait - wait until the me(hw) has turned ready * or timeout is reached * * @dev: mei device * Return: 0 on success, error otherwise */ static int mei_me_hw_ready_wait(struct mei_device *dev) { … } /** * mei_me_check_fw_reset - check for the firmware reset error and exception conditions * * @dev: mei device */ static void mei_me_check_fw_reset(struct mei_device *dev) { … } /** * mei_me_hw_start - hw start routine * * @dev: mei device * Return: 0 on success, error otherwise */ static int mei_me_hw_start(struct mei_device *dev) { … } /** * mei_hbuf_filled_slots - gets number of device filled buffer slots * * @dev: the device structure * * Return: number of filled slots */ static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) { … } /** * mei_me_hbuf_is_empty - checks if host buffer is empty. * * @dev: the device structure * * Return: true if empty, false - otherwise. */ static bool mei_me_hbuf_is_empty(struct mei_device *dev) { … } /** * mei_me_hbuf_empty_slots - counts write empty slots. * * @dev: the device structure * * Return: -EOVERFLOW if overflow, otherwise empty slots count */ static int mei_me_hbuf_empty_slots(struct mei_device *dev) { … } /** * mei_me_hbuf_depth - returns depth of the hw buffer. * * @dev: the device structure * * Return: size of hw buffer in slots */ static u32 mei_me_hbuf_depth(const struct mei_device *dev) { … } /** * mei_me_hbuf_write - writes a message to host hw buffer. * * @dev: the device structure * @hdr: header of message * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes) * @data: payload * @data_len: payload length in bytes * * Return: 0 if success, < 0 - otherwise. */ static int mei_me_hbuf_write(struct mei_device *dev, const void *hdr, size_t hdr_len, const void *data, size_t data_len) { … } /** * mei_me_count_full_read_slots - counts read full slots. * * @dev: the device structure * * Return: -EOVERFLOW if overflow, otherwise filled slots count */ static int mei_me_count_full_read_slots(struct mei_device *dev) { … } /** * mei_me_read_slots - reads a message from mei device. * * @dev: the device structure * @buffer: message buffer will be written * @buffer_length: message size will be read * * Return: always 0 */ static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, unsigned long buffer_length) { … } /** * mei_me_pg_set - write pg enter register * * @dev: the device structure */ static void mei_me_pg_set(struct mei_device *dev) { … } /** * mei_me_pg_unset - write pg exit register * * @dev: the device structure */ static void mei_me_pg_unset(struct mei_device *dev) { … } /** * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) { … } /** * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) { … } /** * mei_me_pg_in_transition - is device now in pg transition * * @dev: the device structure * * Return: true if in pg transition, false otherwise */ static bool mei_me_pg_in_transition(struct mei_device *dev) { … } /** * mei_me_pg_is_enabled - detect if PG is supported by HW * * @dev: the device structure * * Return: true is pg supported, false otherwise */ static bool mei_me_pg_is_enabled(struct mei_device *dev) { … } /** * mei_me_d0i3_set - write d0i3 register bit on mei device. * * @dev: the device structure * @intr: ask for interrupt * * Return: D0I3C register value */ static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) { … } /** * mei_me_d0i3_unset - clean d0i3 register bit on mei device. * * @dev: the device structure * * Return: D0I3C register value */ static u32 mei_me_d0i3_unset(struct mei_device *dev) { … } /** * mei_me_d0i3_enter_sync - perform d0i3 entry procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ static int mei_me_d0i3_enter_sync(struct mei_device *dev) { … } /** * mei_me_d0i3_enter - perform d0i3 entry procedure * no hbm PG handshake * no waiting for confirmation; runs with interrupts * disabled * * @dev: the device structure * * Return: 0 on success an error code otherwise */ static int mei_me_d0i3_enter(struct mei_device *dev) { … } /** * mei_me_d0i3_exit_sync - perform d0i3 exit procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ static int mei_me_d0i3_exit_sync(struct mei_device *dev) { … } /** * mei_me_pg_legacy_intr - perform legacy pg processing * in interrupt thread handler * * @dev: the device structure */ static void mei_me_pg_legacy_intr(struct mei_device *dev) { … } /** * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler * * @dev: the device structure * @intr_source: interrupt source */ static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) { … } /** * mei_me_pg_intr - perform pg processing in interrupt thread handler * * @dev: the device structure * @intr_source: interrupt source */ static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) { … } /** * mei_me_pg_enter_sync - perform runtime pm entry procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ int mei_me_pg_enter_sync(struct mei_device *dev) { … } /** * mei_me_pg_exit_sync - perform runtime pm exit procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ int mei_me_pg_exit_sync(struct mei_device *dev) { … } /** * mei_me_hw_reset - resets fw via mei csr register. * * @dev: the device structure * @intr_enable: if interrupt should be enabled after reset. * * Return: 0 on success an error code otherwise */ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) { … } /** * mei_me_irq_quick_handler - The ISR of the MEI device * * @irq: The irq number * @dev_id: pointer to the device structure * * Return: irqreturn_t */ irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) { … } EXPORT_SYMBOL_GPL(…); /** * mei_me_irq_thread_handler - function called after ISR to handle the interrupt * processing. * * @irq: The irq number * @dev_id: pointer to the device structure * * Return: irqreturn_t * */ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) { … } EXPORT_SYMBOL_GPL(…); #define MEI_POLLING_TIMEOUT_ACTIVE … #define MEI_POLLING_TIMEOUT_IDLE … /** * mei_me_polling_thread - interrupt register polling thread * * @_dev: mei device * * The thread monitors the interrupt source register and calls * mei_me_irq_thread_handler() to handle the firmware * input. * * The function polls in MEI_POLLING_TIMEOUT_ACTIVE timeout * in case there was an event, in idle case the polling * time increases yet again by MEI_POLLING_TIMEOUT_ACTIVE * up to MEI_POLLING_TIMEOUT_IDLE. * * Return: always 0 */ int mei_me_polling_thread(void *_dev) { … } EXPORT_SYMBOL_GPL(…); static const struct mei_hw_ops mei_me_hw_ops = …; /** * mei_me_fw_type_nm() - check for nm sku * * @pdev: pci device * * Read ME FW Status register to check for the Node Manager (NM) Firmware. * The NM FW is only signaled in PCI function 0. * __Note__: Deprecated by PCH8 and newer. * * Return: true in case of NM firmware */ static bool mei_me_fw_type_nm(const struct pci_dev *pdev) { … } #define MEI_CFG_FW_NM … /** * mei_me_fw_type_sps_4() - check for sps 4.0 sku * * @pdev: pci device * * Read ME FW Status register to check for SPS Firmware. * The SPS FW is only signaled in the PCI function 0. * __Note__: Deprecated by SPS 5.0 and newer. * * Return: true in case of SPS firmware */ static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev) { … } #define MEI_CFG_FW_SPS_4 … /** * mei_me_fw_type_sps_ign() - check for sps or ign sku * * @pdev: pci device * * Read ME FW Status register to check for SPS or IGN Firmware. * The SPS/IGN FW is only signaled in pci function 0 * * Return: true in case of SPS/IGN firmware */ static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev) { … } #define MEI_CFG_KIND_ITOUCH … #define MEI_CFG_TYPE_GSC … #define MEI_CFG_TYPE_GSCFI … #define MEI_CFG_FW_SPS_IGN … #define MEI_CFG_FW_VER_SUPP … #define MEI_CFG_ICH_HFS … #define MEI_CFG_ICH10_HFS … #define MEI_CFG_PCH_HFS … #define MEI_CFG_PCH8_HFS … #define MEI_CFG_DMA_128 … #define MEI_CFG_TRC … /* ICH Legacy devices */ static const struct mei_cfg mei_me_ich_cfg = …; /* ICH devices */ static const struct mei_cfg mei_me_ich10_cfg = …; /* PCH6 devices */ static const struct mei_cfg mei_me_pch6_cfg = …; /* PCH7 devices */ static const struct mei_cfg mei_me_pch7_cfg = …; /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = …; /* PCH8 Lynx Point and newer devices */ static const struct mei_cfg mei_me_pch8_cfg = …; /* PCH8 Lynx Point and newer devices - iTouch */ static const struct mei_cfg mei_me_pch8_itouch_cfg = …; /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ static const struct mei_cfg mei_me_pch8_sps_4_cfg = …; /* LBG with quirk for SPS (4.0) Firmware exclusion */ static const struct mei_cfg mei_me_pch12_sps_4_cfg = …; /* Cannon Lake and newer devices */ static const struct mei_cfg mei_me_pch12_cfg = …; /* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */ static const struct mei_cfg mei_me_pch12_sps_cfg = …; /* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion * w/o DMA support. */ static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = …; /* Tiger Lake and newer devices */ static const struct mei_cfg mei_me_pch15_cfg = …; /* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */ static const struct mei_cfg mei_me_pch15_sps_cfg = …; /* Graphics System Controller */ static const struct mei_cfg mei_me_gsc_cfg = …; /* Graphics System Controller Firmware Interface */ static const struct mei_cfg mei_me_gscfi_cfg = …; /* * mei_cfg_list - A list of platform platform specific configurations. * Note: has to be synchronized with enum mei_cfg_idx. */ static const struct mei_cfg *const mei_cfg_list[] = …; const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) { … } EXPORT_SYMBOL_GPL(…); /** * mei_me_dev_init - allocates and initializes the mei device structure * * @parent: device associated with physical device (pci/platform) * @cfg: per device generation config * @slow_fw: configure longer timeouts as FW is slow * * Return: The mei_device pointer on success, NULL on failure. */ struct mei_device *mei_me_dev_init(struct device *parent, const struct mei_cfg *cfg, bool slow_fw) { … } EXPORT_SYMBOL_GPL(…);
Codebase Browser
linux