/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (c) 2013-2014, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ #ifndef _MEI_HW_TXE_REGS_H_ #define _MEI_HW_TXE_REGS_H_ #include "hw.h" #define SEC_ALIVENESS_TIMER_TIMEOUT … #define SEC_ALIVENESS_WAIT_TIMEOUT … #define SEC_RESET_WAIT_TIMEOUT … #define SEC_READY_WAIT_TIMEOUT … #define START_MESSAGE_RESPONSE_WAIT_TIMEOUT … #define RESET_CANCEL_WAIT_TIMEOUT … enum { … }; /* SeC FW Status Register * * FW uses this register in order to report its status to host. * This register resides in PCI-E config space. */ #define PCI_CFG_TXE_FW_STS0 … #define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK … #define PCI_CFG_TXE_FW_STS0_OP_ST_MSK … #define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT … #define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK … #define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK … #define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK … #define PCI_CFG_TXE_FW_STS1 … #define IPC_BASE_ADDR … /* IPC Input Doorbell Register */ #define SEC_IPC_INPUT_DOORBELL_REG … /* IPC Input Status Register * This register indicates whether or not processing of * the most recent command has been completed by the SEC * New commands and payloads should not be written by the Host * until this indicates that the previous command has been processed. */ #define SEC_IPC_INPUT_STATUS_REG … #define SEC_IPC_INPUT_STATUS_RDY … /* IPC Host Interrupt Status Register */ #define SEC_IPC_HOST_INT_STATUS_REG … #define SEC_IPC_HOST_INT_STATUS_OUT_DB … #define SEC_IPC_HOST_INT_STATUS_IN_RDY … #define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD … #define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS … #define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR … #define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR … #define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW … /* Convenient mask for pending interrupts */ #define SEC_IPC_HOST_INT_STATUS_PENDING … /* IPC Host Interrupt Mask Register */ #define SEC_IPC_HOST_INT_MASK_REG … #define SEC_IPC_HOST_INT_MASK_OUT_DB … #define SEC_IPC_HOST_INT_MASK_IN_RDY … /* IPC Input Payload RAM */ #define SEC_IPC_INPUT_PAYLOAD_REG … /* IPC Shared Payload RAM */ #define IPC_SHARED_PAYLOAD_REG … /* SeC Address Translation Table Entry 2 - Ctrl * * This register resides also in SeC's PCI-E Memory space. */ #define SATT2_CTRL_REG … #define SATT2_CTRL_VALID_MSK … #define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT … #define SATT2_CTRL_BRIDGE_HOST_EN_MSK … /* SATT Table Entry 2 SAP Base Address Register */ #define SATT2_SAP_BA_REG … /* SATT Table Entry 2 SAP Size Register. */ #define SATT2_SAP_SIZE_REG … /* SATT Table Entry 2 SAP Bridge Address - LSB Register */ #define SATT2_BRG_BA_LSB_REG … /* Host High-level Interrupt Status Register */ #define HHISR_REG … /* Host High-level Interrupt Enable Register * * Resides in PCI memory space. This is the top hierarchy for * interrupts from SeC to host, aggregating both interrupts that * arrive through HICR registers as well as interrupts * that arrive via IPC. */ #define HHIER_REG … #define IPC_HHIER_SEC … #define IPC_HHIER_BRIDGE … #define IPC_HHIER_MSK … /* Host High-level Interrupt Mask Register. * * Resides in PCI memory space. * This is the top hierarchy for masking interrupts from SeC to host. */ #define HHIMR_REG … #define IPC_HHIMR_SEC … #define IPC_HHIMR_BRIDGE … /* Host High-level IRQ Status Register */ #define HHIRQSR_REG … /* Host Interrupt Cause Register 0 - SeC IPC Readiness * * This register is both an ICR to Host from PCI Memory Space * and it is also exposed in the SeC memory space. * This register is used by SeC's IPC driver in order * to synchronize with host about IPC interface state. */ #define HICR_SEC_IPC_READINESS_REG … #define HICR_SEC_IPC_READINESS_HOST_RDY … #define HICR_SEC_IPC_READINESS_SEC_RDY … #define HICR_SEC_IPC_READINESS_SYS_RDY … #define HICR_SEC_IPC_READINESS_RDY_CLR … /* Host Interrupt Cause Register 1 - Aliveness Response */ /* This register is both an ICR to Host from PCI Memory Space * and it is also exposed in the SeC memory space. * The register may be used by SeC to ACK a host request for aliveness. */ #define HICR_HOST_ALIVENESS_RESP_REG … #define HICR_HOST_ALIVENESS_RESP_ACK … /* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */ #define HICR_SEC_IPC_OUTPUT_DOORBELL_REG … /* Host Interrupt Status Register. * * Resides in PCI memory space. * This is the main register involved in generating interrupts * from SeC to host via HICRs. * The interrupt generation rules are as follows: * An interrupt will be generated whenever for any i, * there is a transition from a state where at least one of * the following conditions did not hold, to a state where * ALL the following conditions hold: * A) HISR.INT[i]_STS == 1. * B) HIER.INT[i]_EN == 1. */ #define HISR_REG … #define HISR_INT_0_STS … #define HISR_INT_1_STS … #define HISR_INT_2_STS … #define HISR_INT_3_STS … #define HISR_INT_4_STS … #define HISR_INT_5_STS … #define HISR_INT_6_STS … #define HISR_INT_7_STS … #define HISR_INT_STS_MSK … /* Host Interrupt Enable Register. Resides in PCI memory space. */ #define HIER_REG … #define HIER_INT_0_EN … #define HIER_INT_1_EN … #define HIER_INT_2_EN … #define HIER_INT_3_EN … #define HIER_INT_4_EN … #define HIER_INT_5_EN … #define HIER_INT_6_EN … #define HIER_INT_7_EN … #define HIER_INT_EN_MSK … /* SEC Memory Space IPC output payload. * * This register is part of the output payload which SEC provides to host. */ #define BRIDGE_IPC_OUTPUT_PAYLOAD_REG … /* SeC Interrupt Cause Register - Host Aliveness Request * This register is both an ICR to SeC and it is also exposed * in the host-visible PCI memory space. * The register is used by host to request SeC aliveness. */ #define SICR_HOST_ALIVENESS_REQ_REG … #define SICR_HOST_ALIVENESS_REQ_REQUESTED … /* SeC Interrupt Cause Register - Host IPC Readiness * * This register is both an ICR to SeC and it is also exposed * in the host-visible PCI memory space. * This register is used by the host's SeC driver uses in order * to synchronize with SeC about IPC interface state. */ #define SICR_HOST_IPC_READINESS_REQ_REG … #define SICR_HOST_IPC_READINESS_HOST_RDY … #define SICR_HOST_IPC_READINESS_SEC_RDY … #define SICR_HOST_IPC_READINESS_SYS_RDY … #define SICR_HOST_IPC_READINESS_RDY_CLR … /* SeC Interrupt Cause Register - SeC IPC Output Status * * This register indicates whether or not processing of the most recent * command has been completed by the Host. * New commands and payloads should not be written by SeC until this * register indicates that the previous command has been processed. */ #define SICR_SEC_IPC_OUTPUT_STATUS_REG … #define SEC_IPC_OUTPUT_STATUS_RDY … /* MEI IPC Message payload size 64 bytes */ #define PAYLOAD_SIZE … /* MAX size for SATT range 32MB */ #define SATT_RANGE_MAX … #endif /* _MEI_HW_TXE_REGS_H_ */
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