/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __CARD_DDCB_H__ #define __CARD_DDCB_H__ /** * IBM Accelerator Family 'GenWQE' * * (C) Copyright IBM Corp. 2013 * * Author: Frank Haverkamp <[email protected]> * Author: Joerg-Stephan Vogt <[email protected]> * Author: Michael Jung <[email protected]> * Author: Michael Ruettger <[email protected]> */ #include <linux/types.h> #include <asm/byteorder.h> #include "genwqe_driver.h" #include "card_base.h" /** * struct ddcb - Device Driver Control Block DDCB * @hsi: Hardware software interlock * @shi: Software hardware interlock. Hsi and shi are used to interlock * software and hardware activities. We are using a compare and * swap operation to ensure that there are no races when * activating new DDCBs on the queue, or when we need to * purge a DDCB from a running queue. * @acfunc: Accelerator function addresses a unit within the chip * @cmd: Command to work on * @cmdopts_16: Options for the command * @asiv: Input data * @asv: Output data * * The DDCB data format is big endian. Multiple consequtive DDBCs form * a DDCB queue. */ #define ASIV_LENGTH … #define ASIV_LENGTH_ATS … #define ASV_LENGTH … struct ddcb { … } __attribute__((packed)); /* CRC polynomials for DDCB */ #define CRC16_POLYNOMIAL … /* * SHI: Software to Hardware Interlock * This 1 byte field is written by software to interlock the * movement of one queue entry to another with the hardware in the * chip. */ #define DDCB_SHI_INTR … #define DDCB_SHI_PURGE … #define DDCB_SHI_NEXT … /* * HSI: Hardware to Software interlock * This 1 byte field is written by hardware to interlock the movement * of one queue entry to another with the software in the chip. */ #define DDCB_HSI_COMPLETED … #define DDCB_HSI_FETCHED … /* * Accessing HSI/SHI is done 32-bit wide * Normally 16-bit access would work too, but on some platforms the * 16 compare and swap operation is not supported. Therefore * switching to 32-bit such that those platforms will work too. * * iCRC HSI/SHI */ #define DDCB_INTR_BE32 … #define DDCB_PURGE_BE32 … #define DDCB_NEXT_BE32 … #define DDCB_COMPLETED_BE32 … #define DDCB_FETCHED_BE32 … /* Definitions of DDCB presets */ #define DDCB_PRESET_PRE … #define ICRC_LENGTH(n) … #define VCRC_LENGTH(n) … /* * Genwqe Scatter Gather list * Each element has up to 8 entries. * The chaining element is element 0 cause of prefetching needs. */ /* * 0b0110 Chained descriptor. The descriptor is describing the next * descriptor list. */ #define SG_CHAINED … /* * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty * condition. */ #define SG_DATA … /* * 0b0000 Early terminator. This is the last entry on the list * irregardless of the length indicated. */ #define SG_END_LIST … /** * struct sglist - Scatter gather list * @target_addr: Either a dma addr of memory to work on or a * dma addr or a subsequent sglist block. * @len: Length of the data block. * @flags: See above. * * Depending on the command the GenWQE card can use a scatter gather * list to describe the memory it works on. Always 8 sg_entry's form * a block. */ struct sg_entry { … }; #endif /* __CARD_DDCB_H__ */
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