/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) ST-Ericsson SA 2010 * * Author: Rabin Vincent <[email protected]> for ST-Ericsson */ #ifndef __STMPE_H #define __STMPE_H #include <linux/device.h> #include <linux/mfd/core.h> #include <linux/mfd/stmpe.h> #include <linux/printk.h> #include <linux/types.h> extern const struct dev_pm_ops stmpe_dev_pm_ops; #ifdef STMPE_DUMP_BYTES static inline void stmpe_dump_bytes(const char *str, const void *buf, size_t len) { print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len); } #else static inline void stmpe_dump_bytes(const char *str, const void *buf, size_t len) { … } #endif /** * struct stmpe_variant_block - information about block * @cell: base mfd cell * @irq: interrupt number to be added to each IORESOURCE_IRQ * in the cell * @block: block id; used for identification with platform data and for * enable and altfunc callbacks */ struct stmpe_variant_block { … }; /** * struct stmpe_variant_info - variant-specific information * @name: part name * @id_val: content of CHIPID register * @id_mask: bits valid in CHIPID register for comparison with id_val * @num_gpios: number of GPIOS * @af_bits: number of bits used to specify the alternate function * @regs: variant specific registers. * @blocks: list of blocks present on this device * @num_blocks: number of blocks present on this device * @num_irqs: number of internal IRQs available on this device * @enable: callback to enable the specified blocks. * Called with the I/O lock held. * @get_altfunc: callback to get the alternate function number for the * specific block * @enable_autosleep: callback to configure autosleep with specified timeout */ struct stmpe_variant_info { … }; /** * struct stmpe_client_info - i2c or spi specific routines/info * @data: client specific data * @read_byte: read single byte * @write_byte: write single byte * @read_block: read block or multiple bytes * @write_block: write block or multiple bytes * @init: client init routine, called during probe */ struct stmpe_client_info { … }; int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum); void stmpe_remove(struct stmpe *stmpe); #define STMPE_ICR_LSB_HIGH … #define STMPE_ICR_LSB_EDGE … #define STMPE_ICR_LSB_GIM … #define STMPE_SYS_CTRL_RESET … #define STMPE_SYS_CTRL_INT_EN … #define STMPE_SYS_CTRL_INT_HI … /* * STMPE801 */ #define STMPE801_ID … #define STMPE801_NR_INTERNAL_IRQS … #define STMPE801_REG_CHIP_ID … #define STMPE801_REG_VERSION_ID … #define STMPE801_REG_SYS_CTRL … #define STMPE801_REG_GPIO_INT_EN … #define STMPE801_REG_GPIO_INT_STA … #define STMPE801_REG_GPIO_MP_STA … #define STMPE801_REG_GPIO_SET_PIN … #define STMPE801_REG_GPIO_DIR … /* * STMPE811 */ #define STMPE811_ID … #define STMPE811_IRQ_TOUCH_DET … #define STMPE811_IRQ_FIFO_TH … #define STMPE811_IRQ_FIFO_OFLOW … #define STMPE811_IRQ_FIFO_FULL … #define STMPE811_IRQ_FIFO_EMPTY … #define STMPE811_IRQ_TEMP_SENS … #define STMPE811_IRQ_ADC … #define STMPE811_IRQ_GPIOC … #define STMPE811_NR_INTERNAL_IRQS … #define STMPE811_REG_CHIP_ID … #define STMPE811_REG_SYS_CTRL … #define STMPE811_REG_SYS_CTRL2 … #define STMPE811_REG_SPI_CFG … #define STMPE811_REG_INT_CTRL … #define STMPE811_REG_INT_EN … #define STMPE811_REG_INT_STA … #define STMPE811_REG_GPIO_INT_EN … #define STMPE811_REG_GPIO_INT_STA … #define STMPE811_REG_GPIO_SET_PIN … #define STMPE811_REG_GPIO_CLR_PIN … #define STMPE811_REG_GPIO_MP_STA … #define STMPE811_REG_GPIO_DIR … #define STMPE811_REG_GPIO_ED … #define STMPE811_REG_GPIO_RE … #define STMPE811_REG_GPIO_FE … #define STMPE811_REG_GPIO_AF … #define STMPE811_SYS_CTRL_RESET … #define STMPE811_SYS_CTRL2_ADC_OFF … #define STMPE811_SYS_CTRL2_TSC_OFF … #define STMPE811_SYS_CTRL2_GPIO_OFF … #define STMPE811_SYS_CTRL2_TS_OFF … /* * STMPE1600 */ #define STMPE1600_ID … #define STMPE1600_NR_INTERNAL_IRQS … #define STMPE1600_REG_CHIP_ID … #define STMPE1600_REG_SYS_CTRL … #define STMPE1600_REG_IEGPIOR_LSB … #define STMPE1600_REG_IEGPIOR_MSB … #define STMPE1600_REG_ISGPIOR_LSB … #define STMPE1600_REG_ISGPIOR_MSB … #define STMPE1600_REG_GPMR_LSB … #define STMPE1600_REG_GPMR_MSB … #define STMPE1600_REG_GPSR_LSB … #define STMPE1600_REG_GPSR_MSB … #define STMPE1600_REG_GPDR_LSB … #define STMPE1600_REG_GPDR_MSB … #define STMPE1600_REG_GPPIR_LSB … #define STMPE1600_REG_GPPIR_MSB … /* * STMPE1601 */ #define STMPE1601_IRQ_GPIOC … #define STMPE1601_IRQ_PWM3 … #define STMPE1601_IRQ_PWM2 … #define STMPE1601_IRQ_PWM1 … #define STMPE1601_IRQ_PWM0 … #define STMPE1601_IRQ_KEYPAD_OVER … #define STMPE1601_IRQ_KEYPAD … #define STMPE1601_IRQ_WAKEUP … #define STMPE1601_NR_INTERNAL_IRQS … #define STMPE1601_REG_SYS_CTRL … #define STMPE1601_REG_SYS_CTRL2 … #define STMPE1601_REG_ICR_MSB … #define STMPE1601_REG_ICR_LSB … #define STMPE1601_REG_IER_MSB … #define STMPE1601_REG_IER_LSB … #define STMPE1601_REG_ISR_MSB … #define STMPE1601_REG_ISR_LSB … #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB … #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB … #define STMPE1601_REG_INT_STA_GPIO_MSB … #define STMPE1601_REG_INT_STA_GPIO_LSB … #define STMPE1601_REG_CHIP_ID … #define STMPE1601_REG_GPIO_SET_MSB … #define STMPE1601_REG_GPIO_SET_LSB … #define STMPE1601_REG_GPIO_CLR_MSB … #define STMPE1601_REG_GPIO_CLR_LSB … #define STMPE1601_REG_GPIO_MP_MSB … #define STMPE1601_REG_GPIO_MP_LSB … #define STMPE1601_REG_GPIO_SET_DIR_MSB … #define STMPE1601_REG_GPIO_SET_DIR_LSB … #define STMPE1601_REG_GPIO_ED_MSB … #define STMPE1601_REG_GPIO_ED_LSB … #define STMPE1601_REG_GPIO_RE_MSB … #define STMPE1601_REG_GPIO_RE_LSB … #define STMPE1601_REG_GPIO_FE_MSB … #define STMPE1601_REG_GPIO_FE_LSB … #define STMPE1601_REG_GPIO_PU_MSB … #define STMPE1601_REG_GPIO_PU_LSB … #define STMPE1601_REG_GPIO_AF_U_MSB … #define STMPE1601_SYS_CTRL_ENABLE_GPIO … #define STMPE1601_SYS_CTRL_ENABLE_KPC … #define STMPE1601_SYS_CTRL_ENABLE_SPWM … /* The 1601/2403 share the same masks */ #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK … #define STPME1601_AUTOSLEEP_ENABLE … /* * STMPE1801 */ #define STMPE1801_ID … #define STMPE1801_NR_INTERNAL_IRQS … #define STMPE1801_IRQ_KEYPAD_COMBI … #define STMPE1801_IRQ_GPIOC … #define STMPE1801_IRQ_KEYPAD_OVER … #define STMPE1801_IRQ_KEYPAD … #define STMPE1801_IRQ_WAKEUP … #define STMPE1801_REG_CHIP_ID … #define STMPE1801_REG_SYS_CTRL … #define STMPE1801_REG_INT_CTRL_LOW … #define STMPE1801_REG_INT_EN_MASK_LOW … #define STMPE1801_REG_INT_STA_LOW … #define STMPE1801_REG_INT_EN_GPIO_MASK_LOW … #define STMPE1801_REG_INT_EN_GPIO_MASK_MID … #define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH … #define STMPE1801_REG_INT_STA_GPIO_LOW … #define STMPE1801_REG_INT_STA_GPIO_MID … #define STMPE1801_REG_INT_STA_GPIO_HIGH … #define STMPE1801_REG_GPIO_SET_LOW … #define STMPE1801_REG_GPIO_SET_MID … #define STMPE1801_REG_GPIO_SET_HIGH … #define STMPE1801_REG_GPIO_CLR_LOW … #define STMPE1801_REG_GPIO_CLR_MID … #define STMPE1801_REG_GPIO_CLR_HIGH … #define STMPE1801_REG_GPIO_MP_LOW … #define STMPE1801_REG_GPIO_MP_MID … #define STMPE1801_REG_GPIO_MP_HIGH … #define STMPE1801_REG_GPIO_SET_DIR_LOW … #define STMPE1801_REG_GPIO_SET_DIR_MID … #define STMPE1801_REG_GPIO_SET_DIR_HIGH … #define STMPE1801_REG_GPIO_RE_LOW … #define STMPE1801_REG_GPIO_RE_MID … #define STMPE1801_REG_GPIO_RE_HIGH … #define STMPE1801_REG_GPIO_FE_LOW … #define STMPE1801_REG_GPIO_FE_MID … #define STMPE1801_REG_GPIO_FE_HIGH … #define STMPE1801_REG_GPIO_PULL_UP_LOW … #define STMPE1801_REG_GPIO_PULL_UP_MID … #define STMPE1801_REG_GPIO_PULL_UP_HIGH … #define STMPE1801_MSK_INT_EN_KPC … #define STMPE1801_MSK_INT_EN_GPIO … /* * STMPE24xx */ #define STMPE24XX_IRQ_GPIOC … #define STMPE24XX_IRQ_PWM2 … #define STMPE24XX_IRQ_PWM1 … #define STMPE24XX_IRQ_PWM0 … #define STMPE24XX_IRQ_ROT_OVER … #define STMPE24XX_IRQ_ROT … #define STMPE24XX_IRQ_KEYPAD_OVER … #define STMPE24XX_IRQ_KEYPAD … #define STMPE24XX_IRQ_WAKEUP … #define STMPE24XX_NR_INTERNAL_IRQS … #define STMPE24XX_REG_SYS_CTRL … #define STMPE24XX_REG_SYS_CTRL2 … #define STMPE24XX_REG_ICR_MSB … #define STMPE24XX_REG_ICR_LSB … #define STMPE24XX_REG_IER_MSB … #define STMPE24XX_REG_IER_LSB … #define STMPE24XX_REG_ISR_MSB … #define STMPE24XX_REG_ISR_LSB … #define STMPE24XX_REG_IEGPIOR_MSB … #define STMPE24XX_REG_IEGPIOR_CSB … #define STMPE24XX_REG_IEGPIOR_LSB … #define STMPE24XX_REG_ISGPIOR_MSB … #define STMPE24XX_REG_ISGPIOR_CSB … #define STMPE24XX_REG_ISGPIOR_LSB … #define STMPE24XX_REG_CHIP_ID … #define STMPE24XX_REG_GPSR_MSB … #define STMPE24XX_REG_GPSR_CSB … #define STMPE24XX_REG_GPSR_LSB … #define STMPE24XX_REG_GPCR_MSB … #define STMPE24XX_REG_GPCR_CSB … #define STMPE24XX_REG_GPCR_LSB … #define STMPE24XX_REG_GPDR_MSB … #define STMPE24XX_REG_GPDR_CSB … #define STMPE24XX_REG_GPDR_LSB … #define STMPE24XX_REG_GPEDR_MSB … #define STMPE24XX_REG_GPEDR_CSB … #define STMPE24XX_REG_GPEDR_LSB … #define STMPE24XX_REG_GPRER_MSB … #define STMPE24XX_REG_GPRER_CSB … #define STMPE24XX_REG_GPRER_LSB … #define STMPE24XX_REG_GPFER_MSB … #define STMPE24XX_REG_GPFER_CSB … #define STMPE24XX_REG_GPFER_LSB … #define STMPE24XX_REG_GPPUR_MSB … #define STMPE24XX_REG_GPPUR_CSB … #define STMPE24XX_REG_GPPUR_LSB … #define STMPE24XX_REG_GPPDR_MSB … #define STMPE24XX_REG_GPPDR_CSB … #define STMPE24XX_REG_GPPDR_LSB … #define STMPE24XX_REG_GPAFR_U_MSB … #define STMPE24XX_REG_GPMR_MSB … #define STMPE24XX_REG_GPMR_CSB … #define STMPE24XX_REG_GPMR_LSB … #define STMPE24XX_SYS_CTRL_ENABLE_GPIO … #define STMPE24XX_SYSCON_ENABLE_PWM … #define STMPE24XX_SYS_CTRL_ENABLE_KPC … #define STMPE24XX_SYSCON_ENABLE_ROT … #endif
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