// SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2021 Intel Corporation. All rights reserved. */ #include <linux/units.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/device.h> #include <linux/delay.h> #include <linux/pci.h> #include <linux/pci-doe.h> #include <linux/aer.h> #include <cxlpci.h> #include <cxlmem.h> #include <cxl.h> #include "core.h" #include "trace.h" /** * DOC: cxl core pci * * Compute Express Link protocols are layered on top of PCIe. CXL core provides * a set of helpers for CXL interactions which occur via PCIe. */ static unsigned short media_ready_timeout = …; module_param(media_ready_timeout, ushort, 0644); MODULE_PARM_DESC(…) …; struct cxl_walk_context { … }; static int match_add_dports(struct pci_dev *pdev, void *data) { … } /** * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port * @port: cxl_port whose ->uport_dev is the upstream of dports to be enumerated * * Returns a positive number of dports enumerated or a negative error * code. */ int devm_cxl_port_enumerate_dports(struct cxl_port *port) { … } EXPORT_SYMBOL_NS_GPL(…); static int cxl_dvsec_mem_range_valid(struct cxl_dev_state *cxlds, int id) { … } static int cxl_dvsec_mem_range_active(struct cxl_dev_state *cxlds, int id) { … } /* * Wait up to @media_ready_timeout for the device to report memory * active. */ int cxl_await_media_ready(struct cxl_dev_state *cxlds) { … } EXPORT_SYMBOL_NS_GPL(…); static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val) { … } static void clear_mem_enable(void *cxlds) { … } static int devm_cxl_enable_mem(struct device *host, struct cxl_dev_state *cxlds) { … } /* require dvsec ranges to be covered by a locked platform window */ static int dvsec_range_allowed(struct device *dev, void *arg) { … } static void disable_hdm(void *_cxlhdm) { … } static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm) { … } int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, struct cxl_endpoint_dvsec_info *info) { … } EXPORT_SYMBOL_NS_GPL(…); /** * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint * @cxlds: Device state * @cxlhdm: Mapped HDM decoder Capability * @info: Cached DVSEC range registers info * * Try to enable the endpoint's HDM Decoder Capability */ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info) { … } EXPORT_SYMBOL_NS_GPL(…); #define CXL_DOE_TABLE_ACCESS_REQ_CODE … #define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ … #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE … #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA … #define CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE … #define CXL_DOE_TABLE_ACCESS_LAST_ENTRY … #define CXL_DOE_PROTOCOL_TABLE_ACCESS … #define CDAT_DOE_REQ(entry_handle) … static int cxl_cdat_get_length(struct device *dev, struct pci_doe_mb *doe_mb, size_t *length) { … } static int cxl_cdat_read_table(struct device *dev, struct pci_doe_mb *doe_mb, struct cdat_doe_rsp *rsp, size_t *length) { … } static unsigned char cdat_checksum(void *buf, size_t size) { … } /** * read_cdat_data - Read the CDAT data on this port * @port: Port to read data from * * This call will sleep waiting for responses from the DOE mailbox. */ void read_cdat_data(struct cxl_port *port) { … } EXPORT_SYMBOL_NS_GPL(…); static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) { … } static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) { … } /* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy(void __iomem *ras_base, u32 *log) { … } /* * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) { … } static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) { … } #ifdef CONFIG_PCIEAER_CXL static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { … } static void cxl_dport_map_ras(struct cxl_dport *dport) { … } static void cxl_disable_rch_root_ints(struct cxl_dport *dport) { … } /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized * @host: host device for devm operations */ void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) { … } EXPORT_SYMBOL_NS_GPL(…); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { … } static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { … } /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. Clear the * status after copying. * * @aer_base: base address of AER capability block in RCRB * @aer_regs: destination for copying AER capability */ static bool cxl_rch_get_aer_info(void __iomem *aer_base, struct aer_capability_regs *aer_regs) { … } /* Get AER severity. Return false if there is no error. */ static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, int *severity) { … } static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { … } #else static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } #endif void cxl_cor_error_detected(struct pci_dev *pdev) { … } EXPORT_SYMBOL_NS_GPL(…); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { … } EXPORT_SYMBOL_NS_GPL(…); static int cxl_flit_size(struct pci_dev *pdev) { … } /** * cxl_pci_get_latency - calculate the link latency for the PCIe link * @pdev: PCI device * * return: calculated latency or 0 for no latency * * CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation * Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency * LinkProgationLatency is negligible, so 0 will be used * RetimerLatency is assumed to be negligible and 0 will be used * FlitLatency = FlitSize / LinkBandwidth * FlitSize is defined by spec. CXL rev3.0 4.2.1. * 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. * The FlitLatency is converted to picoseconds. */ long cxl_pci_get_latency(struct pci_dev *pdev) { … } static int __cxl_endpoint_decoder_reset_detected(struct device *dev, void *data) { … } bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) { … } EXPORT_SYMBOL_NS_GPL(…); int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { … }
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