/* ******************************************************************************* ** O.S : Linux ** FILE NAME : arcmsr.h ** BY : Nick Cheng ** Description: SCSI RAID Device Driver for ** ARECA RAID Host adapter ******************************************************************************* ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. ** ** Web site: www.areca.com.tw ** E-mail: [email protected] ** ** This program is free software; you can redistribute it and/or modify ** it under the terms of the GNU General Public License version 2 as ** published by the Free Software Foundation. ** This program is distributed in the hope that it will be useful, ** but WITHOUT ANY WARRANTY; without even the implied warranty of ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ** GNU General Public License for more details. ******************************************************************************* ** Redistribution and use in source and binary forms, with or without ** modification, are permitted provided that the following conditions ** are met: ** 1. Redistributions of source code must retain the above copyright ** notice, this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright ** notice, this list of conditions and the following disclaimer in the ** documentation and/or other materials provided with the distribution. ** 3. The name of the author may not be used to endorse or promote products ** derived from this software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ #include <linux/interrupt.h> struct device_attribute; /*The limit of outstanding scsi command that firmware can handle*/ #define ARCMSR_NAME … #define ARCMSR_MAX_FREECCB_NUM … #define ARCMSR_MAX_OUTSTANDING_CMD … #define ARCMSR_DEFAULT_OUTSTANDING_CMD … #define ARCMSR_MIN_OUTSTANDING_CMD … #define ARCMSR_DRIVER_VERSION … #define ARCMSR_SCSI_INITIATOR_ID … #define ARCMSR_MAX_XFER_SECTORS … #define ARCMSR_MAX_XFER_SECTORS_B … #define ARCMSR_MAX_XFER_SECTORS_C … #define ARCMSR_MAX_TARGETID … #define ARCMSR_MAX_TARGETLUN … #define ARCMSR_MAX_CMD_PERLUN … #define ARCMSR_DEFAULT_CMD_PERLUN … #define ARCMSR_MIN_CMD_PERLUN … #define ARCMSR_MAX_QBUFFER … #define ARCMSR_DEFAULT_SG_ENTRIES … #define ARCMSR_MAX_HBB_POSTQUEUE … #define ARCMSR_MAX_ARC1214_POSTQUEUE … #define ARCMSR_MAX_ARC1214_DONEQUEUE … #define ARCMSR_MAX_HBE_DONEQUEUE … #define ARCMSR_MAX_XFER_LEN … #define ARCMSR_CDB_SG_PAGE_LENGTH … #define ARCMST_NUM_MSIX_VECTORS … #ifndef PCI_DEVICE_ID_ARECA_1880 #define PCI_DEVICE_ID_ARECA_1880 … #endif #ifndef PCI_DEVICE_ID_ARECA_1214 #define PCI_DEVICE_ID_ARECA_1214 … #endif #ifndef PCI_DEVICE_ID_ARECA_1203 #define PCI_DEVICE_ID_ARECA_1203 … #endif #ifndef PCI_DEVICE_ID_ARECA_1883 #define PCI_DEVICE_ID_ARECA_1883 … #endif #ifndef PCI_DEVICE_ID_ARECA_1884 #define PCI_DEVICE_ID_ARECA_1884 … #endif #define PCI_DEVICE_ID_ARECA_1886_0 … #define PCI_DEVICE_ID_ARECA_1886 … #define ARCMSR_HOURS … #define ARCMSR_MINUTES … #define ARCMSR_DEFAULT_TIMEOUT … /* ********************************************************************************** ** ********************************************************************************** */ #define ARC_SUCCESS … #define ARC_FAILURE … /* ******************************************************************************* ** split 64bits dma addressing ******************************************************************************* */ #define dma_addr_hi32(addr) … #define dma_addr_lo32(addr) … /* ******************************************************************************* ** MESSAGE CONTROL CODE ******************************************************************************* */ struct CMD_MESSAGE { … }; /* ******************************************************************************* ** IOP Message Transfer Data for user space ******************************************************************************* */ #define ARCMSR_API_DATA_BUFLEN … struct CMD_MESSAGE_FIELD { … }; /* IOP message transfer */ #define ARCMSR_MESSAGE_FAIL … /* DeviceType */ #define ARECA_SATA_RAID … /* FunctionCode */ #define FUNCTION_READ_RQBUFFER … #define FUNCTION_WRITE_WQBUFFER … #define FUNCTION_CLEAR_RQBUFFER … #define FUNCTION_CLEAR_WQBUFFER … #define FUNCTION_CLEAR_ALLQBUFFER … #define FUNCTION_RETURN_CODE_3F … #define FUNCTION_SAY_HELLO … #define FUNCTION_SAY_GOODBYE … #define FUNCTION_FLUSH_ADAPTER_CACHE … #define FUNCTION_GET_FIRMWARE_STATUS … #define FUNCTION_HARDWARE_RESET … /* ARECA IO CONTROL CODE*/ #define ARCMSR_MESSAGE_READ_RQBUFFER … #define ARCMSR_MESSAGE_WRITE_WQBUFFER … #define ARCMSR_MESSAGE_CLEAR_RQBUFFER … #define ARCMSR_MESSAGE_CLEAR_WQBUFFER … #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER … #define ARCMSR_MESSAGE_RETURN_CODE_3F … #define ARCMSR_MESSAGE_SAY_HELLO … #define ARCMSR_MESSAGE_SAY_GOODBYE … #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE … /* ARECA IOCTL ReturnCode */ #define ARCMSR_MESSAGE_RETURNCODE_OK … #define ARCMSR_MESSAGE_RETURNCODE_ERROR … #define ARCMSR_MESSAGE_RETURNCODE_3F … #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON … /* ************************************************************* ** structure for holding DMA address data ************************************************************* */ #define IS_DMA64 … #define IS_SG64_ADDR … struct SG32ENTRY { … }__attribute__ ((packed)); struct SG64ENTRY { … }__attribute__ ((packed)); /* ******************************************************************** ** Q Buffer of IOP Message Transfer ******************************************************************** */ struct QBUFFER { … }; /* ******************************************************************************* ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) ******************************************************************************* */ struct FIRMWARE_INFO { … }; /* signature of set and get firmware config */ #define ARCMSR_SIGNATURE_GET_CONFIG … #define ARCMSR_SIGNATURE_SET_CONFIG … /* message code of inbound message register */ #define ARCMSR_INBOUND_MESG0_NOP … #define ARCMSR_INBOUND_MESG0_GET_CONFIG … #define ARCMSR_INBOUND_MESG0_SET_CONFIG … #define ARCMSR_INBOUND_MESG0_ABORT_CMD … #define ARCMSR_INBOUND_MESG0_STOP_BGRB … #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE … #define ARCMSR_INBOUND_MESG0_START_BGRB … #define ARCMSR_INBOUND_MESG0_CHK331PENDING … #define ARCMSR_INBOUND_MESG0_SYNC_TIMER … /* doorbell interrupt generator */ #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK … #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK … #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK … #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK … /* ccb areca cdb flag */ #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE … #define ARCMSR_CCBPOST_FLAG_IAM_BIOS … #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS … #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 … #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 … /* outbound firmware ok */ #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK … /* ARC-1680 Bus Reset*/ #define ARCMSR_ARC1680_BUS_RESET … /* ARC-1880 Bus Reset*/ #define ARCMSR_ARC1880_RESET_ADAPTER … #define ARCMSR_ARC1880_DiagWrite_ENABLE … /* ************************************************************************ ** SPEC. for Areca Type B adapter ************************************************************************ */ /* ARECA HBB COMMAND for its FIRMWARE */ /* window of "instruction flags" from driver to iop */ #define ARCMSR_DRV2IOP_DOORBELL … #define ARCMSR_DRV2IOP_DOORBELL_MASK … /* window of "instruction flags" from iop to driver */ #define ARCMSR_IOP2DRV_DOORBELL … #define ARCMSR_IOP2DRV_DOORBELL_MASK … /* window of "instruction flags" from iop to driver */ #define ARCMSR_IOP2DRV_DOORBELL_1203 … #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 … /* window of "instruction flags" from driver to iop */ #define ARCMSR_DRV2IOP_DOORBELL_1203 … #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 … /* ARECA FLAG LANGUAGE */ /* ioctl transfer */ #define ARCMSR_IOP2DRV_DATA_WRITE_OK … /* ioctl transfer */ #define ARCMSR_IOP2DRV_DATA_READ_OK … #define ARCMSR_IOP2DRV_CDB_DONE … #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE … #define ARCMSR_DOORBELL_HANDLE_INT … #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN … #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN … /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ #define ARCMSR_MESSAGE_GET_CONFIG … /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ #define ARCMSR_MESSAGE_SET_CONFIG … /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ #define ARCMSR_MESSAGE_ABORT_CMD … /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ #define ARCMSR_MESSAGE_STOP_BGRB … /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ #define ARCMSR_MESSAGE_FLUSH_CACHE … /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ #define ARCMSR_MESSAGE_START_BGRB … #define ARCMSR_MESSAGE_SYNC_TIMER … #define ARCMSR_MESSAGE_START_DRIVER_MODE … #define ARCMSR_MESSAGE_SET_POST_WINDOW … #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE … /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ #define ARCMSR_MESSAGE_FIRMWARE_OK … /* ioctl transfer */ #define ARCMSR_DRV2IOP_DATA_WRITE_OK … /* ioctl transfer */ #define ARCMSR_DRV2IOP_DATA_READ_OK … #define ARCMSR_DRV2IOP_CDB_POSTED … #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED … #define ARCMSR_DRV2IOP_END_OF_INTERRUPT … /* data tunnel buffer between user space program and its firmware */ /* user space data to iop 128bytes */ #define ARCMSR_MESSAGE_WBUFFER … /* iop data to user space 128bytes */ #define ARCMSR_MESSAGE_RBUFFER … /* iop message_rwbuffer for message command */ #define ARCMSR_MESSAGE_RWBUFFER … #define MEM_BASE0(x) … #define MEM_BASE1(x) … /* ************************************************************************ ** SPEC. for Areca HBC adapter ************************************************************************ */ #define ARCMSR_HBC_ISR_THROTTLING_LEVEL … #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE … /* Host Interrupt Mask */ #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK … #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK … #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK … #define ARCMSR_HBCMU_ALL_INTMASKENABLE … /* Host Interrupt Status */ #define ARCMSR_HBCMU_UTILITY_A_ISR … /* ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). */ #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR … /* ** Set if Outbound Doorbell register bits 30:1 have a non-zero ** value. This bit clears only when Outbound Doorbell bits ** 30:1 are ALL clear. Only a write to the Outbound Doorbell ** Clear register clears bits in the Outbound Doorbell register. */ #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR … /* ** Set whenever the Outbound Post List Producer/Consumer ** Register (FIFO) is not empty. It clears when the Outbound ** Post List FIFO is empty. */ #define ARCMSR_HBCMU_SAS_ALL_INT … /* ** This bit indicates a SAS interrupt from a source external to ** the PCIe core. This bit is not maskable. */ /* DoorBell*/ #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK … #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK … /*inbound message 0 ready*/ #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE … /*more than 12 request completed in a time*/ #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING … #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK … /*outbound DATA WRITE isr door bell clear*/ #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR … #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK … /*outbound DATA READ isr door bell clear*/ #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR … /*outbound message 0 ready*/ #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE … /*outbound message cmd isr door bell clear*/ #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR … /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK … /* ******************************************************************************* ** SPEC. for Areca Type D adapter ******************************************************************************* */ #define ARCMSR_ARC1214_CHIP_ID … #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION … #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK … #define ARCMSR_ARC1214_SAMPLE_RESET … #define ARCMSR_ARC1214_RESET_REQUEST … #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS … #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE … #define ARCMSR_ARC1214_INBOUND_MESSAGE0 … #define ARCMSR_ARC1214_INBOUND_MESSAGE1 … #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 … #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 … #define ARCMSR_ARC1214_INBOUND_DOORBELL … #define ARCMSR_ARC1214_OUTBOUND_DOORBELL … #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE … #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW … #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH … #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER … #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW … #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH … #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER … #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER … #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE … #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE … #define ARCMSR_ARC1214_MESSAGE_WBUFFER … #define ARCMSR_ARC1214_MESSAGE_RBUFFER … #define ARCMSR_ARC1214_MESSAGE_RWBUFFER … /* Host Interrupt Mask */ #define ARCMSR_ARC1214_ALL_INT_ENABLE … #define ARCMSR_ARC1214_ALL_INT_DISABLE … /* Host Interrupt Status */ #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR … #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR … /* DoorBell*/ #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY … #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ … /*inbound message 0 ready*/ #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK … /*outbound DATA WRITE isr door bell clear*/ #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK … /*outbound message 0 ready*/ #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE … /*outbound message cmd isr door bell clear*/ /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK … #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR … /* ******************************************************************************* ** SPEC. for Areca Type E adapter ******************************************************************************* */ #define ARCMSR_SIGNATURE_1884 … #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK … #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK … #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE … #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK … #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK … #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE … #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK … #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR … #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR … #define ARCMSR_HBEMU_ALL_INTMASKENABLE … /* ARC-1884 doorbell sync */ #define ARCMSR_HBEMU_DOORBELL_SYNC … #define ARCMSR_ARC188X_RESET_ADAPTER … #define ARCMSR_ARC1884_DiagWrite_ENABLE … /* ******************************************************************************* ** SPEC. for Areca Type F adapter ******************************************************************************* */ #define ARCMSR_SIGNATURE_1886 … // Doorbell and interrupt definition are same as Type E adapter /* ARC-1886 doorbell sync */ #define ARCMSR_HBFMU_DOORBELL_SYNC … //set host rw buffer physical address at inbound message 0, 1 (low,high) #define ARCMSR_HBFMU_DOORBELL_SYNC1 … #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK … #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE … /* ******************************************************************************* ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) ******************************************************************************* */ struct ARCMSR_CDB { … }; /* ******************************************************************************* ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor ******************************************************************************* */ struct MessageUnit_A { … }; struct MessageUnit_B { … }; /* ********************************************************************* ** LSI ********************************************************************* */ struct MessageUnit_C{ … }; /* ********************************************************************* ** Messaging Unit (MU) of Type D processor ********************************************************************* */ struct InBound_SRB { … }; struct OutBound_SRB { … }; struct MessageUnit_D { … }; /* ********************************************************************* ** Messaging Unit (MU) of Type E processor(LSI) ********************************************************************* */ struct MessageUnit_E{ … }; /* ********************************************************************* ** Messaging Unit (MU) of Type F processor(LSI) ********************************************************************* */ struct MessageUnit_F { … }; #define MESG_RW_BUFFER_SIZE … pCompletion_Q; #define ARCMSR_XOR_SEG_SIZE … struct HostRamBuf { … }; struct Xor_sg { … }; struct XorHandle { … }; /* ******************************************************************************* ** Adapter Control Block ******************************************************************************* */ struct AdapterControlBlock { … };/* HW_DEVICE_EXTENSION */ /* ******************************************************************************* ** Command Control Block ** this CCB length must be 32 bytes boundary ******************************************************************************* */ struct CommandControlBlock{ … }; /* ******************************************************************************* ** ARECA SCSI sense data ******************************************************************************* */ struct SENSE_DATA { … }; /* ******************************************************************************* ** Outbound Interrupt Status Register - OISR ******************************************************************************* */ #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG … #define ARCMSR_MU_OUTBOUND_PCI_INT … #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT … #define ARCMSR_MU_OUTBOUND_DOORBELL_INT … #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT … #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT … #define ARCMSR_MU_OUTBOUND_HANDLE_INT … /* ******************************************************************************* ** Outbound Interrupt Mask Register - OIMR ******************************************************************************* */ #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG … #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE … #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE … #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE … #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE … #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE … #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE … extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *); extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *, struct QBUFFER __iomem *); extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *); extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); extern const struct attribute_group *arcmsr_host_groups[]; extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
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