/* SPDX-License-Identifier: GPL-2.0-only */ /* * Aic94xx SAS/SATA driver hardware registers definitions. * * Copyright (C) 2004 Adaptec, Inc. All rights reserved. * Copyright (C) 2004 David Chaw <[email protected]> * Copyright (C) 2005 Luben Tuikov <[email protected]> * * Luben Tuikov: Some register value updates to make it work with the window * agnostic register r/w functions. Some register corrections, sizes, * etc. * * $Id: //depot/aic94xx/aic94xx_reg_def.h#27 $ */ #ifndef _ADP94XX_REG_DEF_H_ #define _ADP94XX_REG_DEF_H_ /* * Common definitions. */ #define CSEQ_MODE_PAGE_SIZE … #define LmSEQ_MODE_PAGE_SIZE … #define LmSEQ_HOST_REG_SIZE … /********************* COM_SAS registers definition *************************/ /* The base is REG_BASE_ADDR, defined in aic94xx_reg.h. */ /* * CHIM Registers, Address Range : (0x00-0xFF) */ #define COMBIST … /* bits 31:24 */ #define L7BLKRST … #define L6BLKRST … #define L5BLKRST … #define L4BLKRST … #define L3BLKRST … #define L2BLKRST … #define L1BLKRST … #define L0BLKRST … #define LmBLKRST … #define LmBLKRST_COMBIST(phyid) … #define OCMBLKRST … #define CTXMEMBLKRST … #define CSEQBLKRST … #define EXSIBLKRST … #define DPIBLKRST … #define DFIFBLKRST … #define HARDRST … #define COMBLKRST … #define FRCDFPERR … #define FRCCIOPERR … #define FRCBISTERR … #define COMBISTEN … #define COMBISTDONE … #define COMBISTFAIL … #define COMSTAT … #define REQMBXREAD … #define RSPMBXAVAIL … #define CSBUFPERR … #define OVLYERR … #define CSERR … #define OVLYDMADONE … #define COMSTAT_MASK … #define COMSTATEN … #define EN_REQMBXREAD … #define EN_RSPMBXAVAIL … #define EN_CSBUFPERR … #define EN_OVLYERR … #define EN_CSERR … #define EN_OVLYDONE … #define SCBPRO … #define SCBCONS_MASK … #define SCBPRO_MASK … #define CHIMREQMBX … #define CHIMRSPMBX … #define CHIMINT … #define EXT_INT0 … #define EXT_INT1 … #define PORRSTDET … #define HARDRSTDET … #define DLAVAILQ … #define HOSTERR … #define INITERR … #define DEVINT … #define COMINT … #define DEVTIMER2 … #define DEVTIMER1 … #define DLAVAIL … #define CHIMINT_MASK … #define DEVEXCEPT_MASK … #define CHIMINTEN … #define RST_EN_EXT_INT1 … #define RST_EN_EXT_INT0 … #define RST_EN_HOSTERR … #define RST_EN_INITERR … #define RST_EN_DEVINT … #define RST_EN_COMINT … #define RST_EN_DEVTIMER2 … #define RST_EN_DEVTIMER1 … #define RST_EN_DLAVAIL … #define SET_EN_EXT_INT1 … #define SET_EN_EXT_INT0 … #define SET_EN_HOSTERR … #define SET_EN_INITERR … #define SET_EN_DEVINT … #define SET_EN_COMINT … #define SET_EN_DEVTIMER2 … #define SET_EN_DEVTIMER1 … #define SET_EN_DLAVAIL … #define RST_CHIMINTEN … #define SET_CHIMINTEN … #define OVLYDMACTL … #define OVLYADR_MASK … #define OVLYLSEQ_MASK … #define OVLYCSEQ … #define OVLYHALTERR … #define PIOCMODE … #define RESETOVLYDMA … #define STARTOVLYDMA … #define STOPOVLYDMA … #define OVLYDMAACT … #define OVLYDMACNT … #define OVLYDOMAIN1 … #define OVLYDOMAIN0 … #define OVLYBUFADR_MASK … #define OVLYDMACNT_MASK … #define OVLYDMAADR … #define DMAERR … #define OVLYERRSTAT_MASK … #define CSERRSTAT_MASK … #define SPIODATA … /* 0x38 - 0x3C are reserved */ #define T1CNTRLR … #define T1DONE … #define TIMER64 … #define T1ENABLE … #define T1RELOAD … #define T1PRESCALER_MASK … #define T1CMPR … #define T1CNTR … #define T2CNTRLR … #define T2DONE … #define T2ENABLE … #define T2RELOAD … #define T2PRESCALER_MASK … #define T2CMPR … #define T2CNTR … /* 0x58h - 0xFCh are reserved */ /* * DCH_SAS Registers, Address Range : (0x800-0xFFF) */ #define CMDCTXBASE … #define DEVCTXBASE … #define CTXDOMAIN … #define DEVCTXDOMAIN1 … #define DEVCTXDOMAIN0 … #define CMDCTXDOMAIN1 … #define CMDCTXDOMAIN0 … #define DCHCTL … #define OCMBISTREPAIR … #define OCMBISTEN … #define OCMBISTDN … #define OCMBISTFAIL … #define DDBBISTEN … #define DDBBISTDN … #define DDBBISTFAIL … #define SCBBISTEN … #define SCBBISTDN … #define SCBBISTFAIL … #define MEMSEL_MASK … #define MEMSEL_CCM_LSEQ … #define MEMSEL_CCM_IOP … #define MEMSEL_CCM_SASCTL … #define MEMSEL_DCM_LSEQ … #define MEMSEL_DCM_IOP … #define MEMSEL_OCM … #define FRCERR … #define AUTORLS … #define DCHREVISION … #define DCHREVISION_MASK … #define DCHSTATUS … #define EN_CFIFTOERR … #define CFIFTOERR … #define CSEQINT … #define LSEQ7INT … #define LSEQ6INT … #define LSEQ5INT … #define LSEQ4INT … #define LSEQ3INT … #define LSEQ2INT … #define LSEQ1INT … #define LSEQ0INT … #define LSEQINT_MASK … #define DCHDFIFDEBUG … #define ENFAIRMST … #define DISWRMST9 … #define DISWRMST8 … #define DISRDMST … #define ATOMICSTATCTL … /* 8 bit wide */ #define AUTOINC … #define ATOMICERR … #define ATOMICWIN … #define ATOMICDONE … #define ALTCIOADR … /* 16 bit; bits 8:0 define CIO addr space of CSEQ */ #define ASCBPTR … /* 16 bit wide */ #define ADDBPTR … /* 16 bit wide */ #define ANEWDATA … /* 16 bit */ #define AOLDDATA … /* 16 bit */ #define CTXACCESS … /* 32 bit */ /* 0x83Ch - 0xFFCh are reserved */ /* * ARP2 External Processor Registers, Address Range : (0x00-0x1F) */ #define ARP2CTL … #define FRCSCRPERR … #define FRCARP2PERR … #define FRCARP2ILLOPC … #define ENWAITTO … #define PERRORDIS … #define FAILDIS … #define CIOPERRDIS … #define BREAKEN3 … #define BREAKEN2 … #define BREAKEN1 … #define BREAKEN0 … #define EPAUSE … #define PAUSED … #define STEP … #define ARP2RESET … #define ARP2INT … #define HALTCODE_MASK … #define ARP2WAITTO … #define ARP2HALTC … #define ARP2ILLOPC … #define ARP2PERR … #define ARP2CIOPERR … #define ARP2BREAK3 … #define ARP2BREAK2 … #define ARP2BREAK1 … #define ARP2BREAK0 … #define ARP2INTEN … #define EN_ARP2WAITTO … #define EN_ARP2HALTC … #define EN_ARP2ILLOPC … #define EN_ARP2PERR … #define EN_ARP2CIOPERR … #define EN_ARP2BREAK3 … #define EN_ARP2BREAK2 … #define EN_ARP2BREAK1 … #define EN_ARP2BREAK0 … #define ARP2BREAKADR01 … #define BREAKADR1_MASK … #define BREAKADR0_MASK … #define ARP2BREAKADR23 … #define BREAKADR3_MASK … #define BREAKADR2_MASK … /* 0x14h - 0x1Ch are reserved */ /* * ARP2 Registers, Address Range : (0x00-0x1F) * The definitions have the same address offset for CSEQ and LmSEQ * CIO Bus Registers. */ #define MODEPTR … #define DSTMODE … #define SRCMODE … #define ALTMODE … #define ALTDMODE … #define ALTSMODE … #define ATOMICXCHG … #define FLAG … #define INTCODE_MASK … #define ALTMODEV2 … #define CARRY_INT … #define CARRY … #define ARP2INTCTL … #define PAUSEDIS … #define RSTINTCTL … #define POPALTMODE … #define ALTMODEV … #define INTMASK … #define IRET … #define STACK … #define FUNCTION1 … #define PRGMCNT … #define ACCUM … #define SINDEX … #define DINDEX … #define ALLONES … #define ALLZEROS … #define SINDIR … #define DINDIR … #define JUMLDIR … #define ARP2HALTCODE … #define CURRADDR … #define LASTADDR … #define NXTLADDR … #define DBGPORTPTR … #define DBGPORT … /* * CIO Registers. * The definitions have the same address offset for CSEQ and LmSEQ * CIO Bus Registers. */ #define MnSCBPTR … #define MnDDBPTR … #define SCRATCHPAGE … #define MnSCRATCHPAGE … #define SCRATCHPAGESV … #define MnSCRATCHPAGESV … #define MnDMAERRS … #define MnSGDMAERRS … #define MnSGBUF … #define MnSGDMASTAT … #define MnDDMACTL … #define MnDDMASTAT … #define MnDDMAMODE … #define MnDMAENG … #define MnPIPECTL … #define MnSGBADR … #define MnSCB_SITE … #define MnDDB_SITE … /* * The common definitions below have the same address offset for both * CSEQ and LmSEQ. */ #define BISTCTL0 … #define BISTCTL1 … #define MAPPEDSCR … /* * CSEQ Host Register, Address Range : (0x000-0xFFC) */ #define CSEQ_HOST_REG_BASE_ADR … #define CARP2CTL … #define CARP2INT … #define CARP2INTEN … #define CARP2BREAKADR01 … #define CARP2BREAKADR23 … #define CBISTCTL … #define CSEQRAMBISTEN … #define CSEQRAMBISTDN … #define CSEQRAMBISTFAIL … #define CSEQSCRBISTEN … #define CSEQSCRBISTDN … #define CSEQSCRBISTFAIL … #define CMAPPEDSCR … /* * CSEQ CIO Bus Registers, Address Range : (0x0000-0x1FFC) * 16 modes, each mode is 512 bytes. * Unless specified, the register should valid for all modes. */ #define CSEQ_CIO_REG_BASE_ADR … #define CSEQm_CIO_REG(Mode, Reg) … #define CMODEPTR … #define CALTMODE … #define CATOMICXCHG … #define CFLAG … #define CARP2INTCTL … #define CSTACK … #define CFUNCTION1 … #define CPRGMCNT … #define CACCUM … #define CSINDEX … #define CDINDEX … #define CALLONES … #define CALLZEROS … #define CSINDIR … #define CDINDIR … #define CJUMLDIR … #define CARP2HALTCODE … #define CCURRADDR … #define CLASTADDR … #define CNXTLADDR … #define CDBGPORTPTR … #define CDBGPORT … #define CSCRATCHPAGE … #define CMnSCBPTR(Mode) … #define CMnDDBPTR(Mode) … #define CMnSCRATCHPAGE(Mode) … #define CLINKCON … #define CCIOAACESS … /* mode 0-7 */ #define MnREQMBX … #define CMnREQMBX(Mode) … /* mode 8 */ #define CSEQCON … /* mode 0-7 */ #define MnRSPMBX … #define CMnRSPMBX(Mode) … /* mode 8 */ #define CSEQCOMCTL … /* mode 8 */ #define CSEQCOMSTAT … /* mode 8 */ #define CSEQCOMINTEN … /* mode 8 */ #define CSEQCOMDMACTL … #define CSHALTERR … #define RESETCSDMA … #define STARTCSDMA … #define STOPCSDMA … #define CSDMAACT … /* mode 0-7 */ #define MnINT … #define CMnINT(Mode) … #define CMnREQMBXE … #define CMnRSPMBXF … #define CMnINT_MASK … /* mode 8 */ #define CSEQREQMBX … /* mode 0-7 */ #define MnINTEN … #define CMnINTEN(Mode) … #define EN_CMnRSPMBXF … /* mode 8 */ #define CSEQRSPMBX … /* mode 8 */ #define CSDMAADR … /* mode 8 */ #define CSDMACNT … /* mode 8 */ #define CSEQDLCTL … #define DONELISTEND … #define DONELISTSIZE_MASK … #define DONELISTSIZE_8ELEM … #define DONELISTSIZE_16ELEM … #define DONELISTSIZE_32ELEM … #define DONELISTSIZE_64ELEM … #define DONELISTSIZE_128ELEM … #define DONELISTSIZE_256ELEM … #define DONELISTSIZE_512ELEM … #define DONELISTSIZE_1024ELEM … #define DONELISTSIZE_2048ELEM … #define DONELISTSIZE_4096ELEM … #define DONELISTSIZE_8192ELEM … #define DONELISTSIZE_16384ELEM … /* mode 8 */ #define CSEQDLOFFS … /* mode 11 */ #define CM11INTVEC0 … /* mode 11 */ #define CM11INTVEC1 … /* mode 11 */ #define CM11INTVEC2 … #define CCONMSK … #define CCONEXIST … #define CCONMODE … #define CTIMERCALC … #define CINTDIS … /* mode 8, 32x32 bits, 128 bytes of mapped buffer */ #define CSBUFFER … #define CSCRATCH … /* mode 0-8 */ #define CMnSCRATCH(Mode) … /* * CSEQ Mapped Instruction RAM Page, Address Range : (0x0000-0x1FFC) */ #define CSEQ_RAM_REG_BASE_ADR … /* * The common definitions below have the same address offset for all the Link * sequencers. */ #define MODECTL … #define DBGMODE … #define CONTROL … #define LEDTIMER … #define LEDTIMERS_10us … #define LEDTIMERS_1ms … #define LEDTIMERS_100ms … #define LEDMODE_TXRX … #define LEDMODE_CONNECTED … #define LEDPOL … #define LSEQRAM … /* * LmSEQ Host Registers, Address Range : (0x0000-0x3FFC) */ #define LSEQ0_HOST_REG_BASE_ADR … #define LSEQ1_HOST_REG_BASE_ADR … #define LSEQ2_HOST_REG_BASE_ADR … #define LSEQ3_HOST_REG_BASE_ADR … #define LSEQ4_HOST_REG_BASE_ADR … #define LSEQ5_HOST_REG_BASE_ADR … #define LSEQ6_HOST_REG_BASE_ADR … #define LSEQ7_HOST_REG_BASE_ADR … #define LmARP2CTL(LinkNum) … #define LmARP2INT(LinkNum) … #define LmARP2INTEN(LinkNum) … #define LmDBGMODE(LinkNum) … #define LmCONTROL(LinkNum) … #define LmARP2BREAKADR01(LinkNum) … #define LmARP2BREAKADR23(LinkNum) … #define LmMODECTL(LinkNum) … #define LmAUTODISCI … #define LmDSBLBITLT … #define LmDSBLANTT … #define LmDSBLCRTT … #define LmDSBLCONT … #define LmPRIMODE … #define LmDSBLHOLD … #define LmDISACK … #define LmBLIND48 … #define LmRCVMODE_MASK … #define LmRCVMODE_PLD … #define LmRCVMODE_HPC … #define LmDBGMODE(LinkNum) … #define LmFRCPERR … #define LmMEMSEL_MASK … #define LmFRCRBPERR … #define LmFRCTBPERR … #define LmFRCSGBPERR … #define LmFRCARBPERR … #define LmRCVIDW … #define LmINVDWERR … #define LmRCVDISP … #define LmDISPERR … #define LmDSBLDSCR … #define LmDSBLSCR … #define LmFRCNAK … #define LmFRCROFS … #define LmFRCCRC … #define LmFRMTYPE_MASK … #define LmSG_DATA … #define LmSG_COMMAND … #define LmSG_TASK … #define LmSG_TGTXFER … #define LmSG_RESPONSE … #define LmSG_IDENADDR … #define LmSG_OPENADDR … #define LmDISCRCGEN … #define LmDISCRCCHK … #define LmSSXMTFRM … #define LmSSRCVFRM … #define LmCONTROL(LinkNum) … #define LmSTEPXMTFRM … #define LmSTEPRCVFRM … #define LmBISTCTL0(LinkNum) … #define ARBBISTEN … #define ARBBISTDN … #define ARBBISTFAIL … #define TBBISTEN … #define TBBISTDN … #define TBBISTFAIL … #define RBBISTEN … #define RBBISTDN … #define RBBISTFAIL … #define SGBISTEN … #define SGBISTDN … #define SGBISTFAIL … #define LmBISTCTL1(LinkNum) … #define LmRAMPAGE1 … #define LmRAMPAGE0 … #define LmIMEMBISTEN … #define LmIMEMBISTDN … #define LmIMEMBISTFAIL … #define LmSCRBISTEN … #define LmSCRBISTDN … #define LmSCRBISTFAIL … #define LmRAMPAGE … #define LmRAMPAGE_LSHIFT … #define LmSCRATCH(LinkNum) … #define LmSEQRAM(LinkNum) … /* * LmSEQ CIO Bus Register, Address Range : (0x0000-0xFFC) * 8 modes, each mode is 512 bytes. * Unless specified, the register should valid for all modes. */ #define LmSEQ_CIOBUS_REG_BASE … #define LmSEQ_PHY_BASE(Mode, LinkNum) … #define LmSEQ_PHY_REG(Mode, LinkNum, Reg) … #define LmMODEPTR(LinkNum) … #define LmALTMODE(LinkNum) … #define LmATOMICXCHG(LinkNum) … #define LmFLAG(LinkNum) … #define LmARP2INTCTL(LinkNum) … #define LmSTACK(LinkNum) … #define LmFUNCTION1(LinkNum) … #define LmPRGMCNT(LinkNum) … #define LmACCUM(LinkNum) … #define LmSINDEX(LinkNum) … #define LmDINDEX(LinkNum) … #define LmALLONES(LinkNum) … #define LmALLZEROS(LinkNum) … #define LmSINDIR(LinkNum) … #define LmDINDIR(LinkNum) … #define LmJUMLDIR(LinkNum) … #define LmARP2HALTCODE(LinkNum) … #define LmCURRADDR(LinkNum) … #define LmLASTADDR(LinkNum) … #define LmNXTLADDR(LinkNum) … #define LmDBGPORTPTR(LinkNum) … #define LmDBGPORT(LinkNum) … #define LmSCRATCHPAGE(LinkNum) … #define LmMnSCRATCHPAGE(LinkNum, Mode) … #define LmTIMERCALC(LinkNum) … #define LmREQMBX(LinkNum) … #define LmRSPMBX(LinkNum) … #define LmMnINT(LinkNum, Mode) … #define CTXMEMSIZE … #define LmACKREQ … #define LmNAKREQ … #define LmMnXMTERR … #define LmM5OOBSVC … #define LmHWTINT … #define LmMnCTXDONE … #define LmM2REQMBXF … #define LmM2RSPMBXE … #define LmMnDMAERR … #define LmRCVPRIM … #define LmRCVERR … #define LmADDRRCV … #define LmMnHDRMISS … #define LmMnWAITSCB … #define LmMnRLSSCB … #define LmMnSAVECTX … #define LmMnFETCHSG … #define LmMnLOADCTX … #define LmMnCFGICL … #define LmMnCFGSATA … #define LmMnCFGEXPSATA … #define LmMnCFGCMPLT … #define LmMnCFGRBUF … #define LmMnSAVETTR … #define LmMnCFGRDAT … #define LmMnCFGHDR … #define LmMnINTEN(LinkNum, Mode) … #define EN_LmACKREQ … #define EN_LmNAKREQ … #define EN_LmMnXMTERR … #define EN_LmM5OOBSVC … #define EN_LmHWTINT … #define EN_LmMnCTXDONE … #define EN_LmM2REQMBXF … #define EN_LmM2RSPMBXE … #define EN_LmMnDMAERR … #define EN_LmRCVPRIM … #define EN_LmRCVERR … #define EN_LmADDRRCV … #define EN_LmMnHDRMISS … #define EN_LmMnWAITSCB … #define EN_LmMnRLSSCB … #define EN_LmMnSAVECTX … #define EN_LmMnFETCHSG … #define EN_LmMnLOADCTX … #define EN_LmMnCFGICL … #define EN_LmMnCFGSATA … #define EN_LmMnCFGEXPSATA … #define EN_LmMnCFGCMPLT … #define EN_LmMnCFGRBUF … #define EN_LmMnSAVETTR … #define EN_LmMnCFGRDAT … #define EN_LmMnCFGHDR … #define LmM0INTEN_MASK … #define LmM1INTEN_MASK … #define LmM2INTEN_MASK … #define LmM5INTEN_MASK … #define LmXMTPRIMD(LinkNum) … #define LmXMTPRIMCS(LinkNum) … #define LmCONSTAT(LinkNum) … #define LmMnDMAERRS(LinkNum, Mode) … #define LmMnSGDMAERRS(LinkNum, Mode) … #define LmM0EXPHDRP(LinkNum) … #define LmM1SASALIGN(LinkNum) … #define SAS_ALIGN_DEFAULT … #define LmM0MSKHDRP(LinkNum) … #define LmM1STPALIGN(LinkNum) … #define STP_ALIGN_DEFAULT … #define LmM0RCVHDRP(LinkNum) … #define LmM1XMTHDRP(LinkNum) … #define LmM0ICLADR(LinkNum) … #define LmM1ALIGNMODE(LinkNum) … #define LmDISALIGN … #define LmROTSTPALIGN … #define LmSTPALIGN … #define LmROTNOTIFY … #define LmDUALALIGN … #define LmROTALIGN … #define LmM0EXPRCVNT(LinkNum) … #define LmM1XMTCNT(LinkNum) … #define LmMnBUFSTAT(LinkNum, Mode) … #define LmMnBUFPERR … /* mode 0-1 */ #define LmMnXFRLVL(LinkNum, Mode) … #define LmMnXFRLVL_128 … #define LmMnXFRLVL_256 … #define LmMnXFRLVL_512 … #define LmMnXFRLVL_1024 … #define LmMnXFRLVL_1536 … #define LmMnXFRLVL_2048 … /* mode 0-1 */ #define LmMnSGDMACTL(LinkNum, Mode) … #define LmMnRESETSG … #define LmMnSTOPSG … #define LmMnSTARTSG … /* mode 0-1 */ #define LmMnSGDMASTAT(LinkNum, Mode) … /* mode 0-1 */ #define LmMnDDMACTL(LinkNum, Mode) … #define LmMnFLUSH … #define LmMnRLSRTRY … #define LmMnDISCARD … #define LmMnRESETDAT … #define LmMnSUSDAT … #define LmMnSTOPDAT … #define LmMnSTARTDAT … /* mode 0-1 */ #define LmMnDDMASTAT(LinkNum, Mode) … #define LmMnDPEMPTY … #define LmMnFLUSHING … #define LmMnDDMAREQ … #define LmMnHDMAREQ … #define LmMnDATFREE … #define LmMnDATSUS … #define LmMnDATACT … #define LmMnDATEN … /* mode 0-1 */ #define LmMnDDMAMODE(LinkNum, Mode) … #define LmMnDMATYPE_NORMAL … #define LmMnDMATYPE_HOST_ONLY_TX … #define LmMnDMATYPE_DEVICE_ONLY_TX … #define LmMnDMATYPE_INVALID … #define LmMnDMATYPE_MASK … #define LmMnDMAWRAP … #define LmMnBITBUCKET … #define LmMnDISHDR … #define LmMnSTPCRC … #define LmXTEST … #define LmMnDISCRC … #define LmMnENINTLK … #define LmMnADDRFRM … #define LmMnENXMTCRC … /* mode 0-1 */ #define LmMnXFRCNT(LinkNum, Mode) … /* mode 0-1 */ #define LmMnDPSEL(LinkNum, Mode) … #define LmMnDPSEL_MASK … #define LmMnEOLPRE … #define LmMnEOSPRE … /* Registers used in conjunction with LmMnDPSEL and LmMnDPACC registers */ /* Receive Mode n = 0 */ #define LmMnHRADDR … #define LmMnHBYTECNT … #define LmMnHREWIND … #define LmMnDWADDR … #define LmMnDSPACECNT … #define LmMnDFRMSIZE … /* Registers used in conjunction with LmMnDPSEL and LmMnDPACC registers */ /* Transmit Mode n = 1 */ #define LmMnHWADDR … #define LmMnHSPACECNT … /* #define LmMnHREWIND 0x02 */ #define LmMnDRADDR … #define LmMnDBYTECNT … /* #define LmMnDFRMSIZE 0x05 */ /* mode 0-1 */ #define LmMnDPACC(LinkNum, Mode) … #define LmMnDPACC_MASK … /* mode 0-1 */ #define LmMnHOLDLVL(LinkNum, Mode) … #define LmPRMSTAT0(LinkNum) … #define LmPRMSTAT0BYTE0 … #define LmPRMSTAT0BYTE1 … #define LmPRMSTAT0BYTE2 … #define LmPRMSTAT0BYTE3 … #define LmFRAMERCVD … #define LmXFRRDYRCVD … #define LmUNKNOWNP … #define LmBREAK … #define LmDONE … #define LmOPENACPT … #define LmOPENRJCT … #define LmOPENRTRY … #define LmCLOSERV1 … #define LmCLOSERV0 … #define LmCLOSENORM … #define LmCLOSECLAF … #define LmNOTIFYRV2 … #define LmNOTIFYRV1 … #define LmNOTIFYRV0 … #define LmNOTIFYSPIN … #define LmBROADRV4 … #define LmBROADRV3 … #define LmBROADRV2 … #define LmBROADRV1 … #define LmBROADSES … #define LmBROADRVCH1 … #define LmBROADRVCH0 … #define LmBROADCH … #define LmAIPRVWP … #define LmAIPWP … #define LmAIPWD … #define LmAIPWC … #define LmAIPRV2 … #define LmAIPRV1 … #define LmAIPRV0 … #define LmAIPNRML … #define LmBROADCAST_MASK … #define LmPRMSTAT1(LinkNum) … #define LmPRMSTAT1BYTE0 … #define LmPRMSTAT1BYTE1 … #define LmPRMSTAT1BYTE2 … #define LmPRMSTAT1BYTE3 … #define LmFRMRCVDSTAT … #define LmBREAK_DET … #define LmCLOSE_DET … #define LmDONE_DET … #define LmXRDY … #define LmSYNCSRST … #define LmSYNC … #define LmXHOLD … #define LmRRDY … #define LmHOLD … #define LmROK … #define LmRIP … #define LmCRBLK … #define LmACK … #define LmNAK … #define LmHARDRST … #define LmERROR … #define LmRERR … #define LmPMREQP … #define LmPMREQS … #define LmPMACK … #define LmPMNAK … #define LmDMAT … /* mode 1 */ #define LmMnSATAFS(LinkNum, Mode) … #define LmMnXMTSIZE(LinkNum, Mode) … /* mode 0 */ #define LmMnFRMERR(LinkNum, Mode) … #define LmACRCERR … #define LmPHYOVRN … #define LmOBOVRN … #define LmMnZERODATA … #define LmSATAINTLK … #define LmMnCRCERR … #define LmRRDYOVRN … #define LmMISSSOAF … #define LmMISSSOF … #define LmMISSEOAF … #define LmMISSEOF … #define LmFRMERREN(LinkNum) … #define EN_LmACRCERR … #define EN_LmPHYOVRN … #define EN_LmOBOVRN … #define EN_LmMnZERODATA … #define EN_LmSATAINTLK … #define EN_LmFRMBAD … #define EN_LmMnCRCERR … #define EN_LmRRDYOVRN … #define EN_LmMISSSOAF … #define EN_LmMISSSOF … #define EN_LmMISSEOAF … #define EN_LmMISSEOF … #define LmFRMERREN_MASK … #define LmHWTSTATEN(LinkNum) … #define EN_LmDONETO … #define EN_LmINVDISP … #define EN_LmINVDW … #define EN_LmDWSEVENT … #define EN_LmCRTTTO … #define EN_LmANTTTO … #define EN_LmBITLTTO … #define LmHWTSTATEN_MASK … #define LmHWTSTAT(LinkNum) … #define LmDONETO … #define LmINVDISP … #define LmINVDW … #define LmDWSEVENT … #define LmCRTTTO … #define LmANTTTO … #define LmBITLTTO … #define LmMnDATABUFADR(LinkNum, Mode) … #define LmDATABUFADR_MASK … #define LmMnDATABUF(LinkNum, Mode) … #define LmPRIMSTAT0EN(LinkNum) … #define EN_LmUNKNOWNP … #define EN_LmBREAK … #define EN_LmDONE … #define EN_LmOPENACPT … #define EN_LmOPENRJCT … #define EN_LmOPENRTRY … #define EN_LmCLOSERV1 … #define EN_LmCLOSERV0 … #define EN_LmCLOSENORM … #define EN_LmCLOSECLAF … #define EN_LmNOTIFYRV2 … #define EN_LmNOTIFYRV1 … #define EN_LmNOTIFYRV0 … #define EN_LmNOTIFYSPIN … #define EN_LmBROADRV4 … #define EN_LmBROADRV3 … #define EN_LmBROADRV2 … #define EN_LmBROADRV1 … #define EN_LmBROADRV0 … #define EN_LmBROADRVCH1 … #define EN_LmBROADRVCH0 … #define EN_LmBROADCH … #define EN_LmAIPRVWP … #define EN_LmAIPWP … #define EN_LmAIPWD … #define EN_LmAIPWC … #define EN_LmAIPRV2 … #define EN_LmAIPRV1 … #define EN_LmAIPRV0 … #define EN_LmAIPNRML … #define LmPRIMSTAT0EN_MASK … #define LmPRIMSTAT1EN(LinkNum) … #define EN_LmXRDY … #define EN_LmSYNCSRST … #define EN_LmSYNC … #define EN_LmXHOLD … #define EN_LmRRDY … #define EN_LmHOLD … #define EN_LmROK … #define EN_LmRIP … #define EN_LmCRBLK … #define EN_LmACK … #define EN_LmNAK … #define EN_LmHARDRST … #define EN_LmERROR … #define EN_LmRERR … #define EN_LmPMREQP … #define EN_LmPMREQS … #define EN_LmPMACK … #define EN_LmPMNAK … #define EN_LmDMAT … #define LmPRIMSTAT1EN_MASK … #define LmSMSTATE(LinkNum) … #define LmSMSTATEBRK(LinkNum) … #define LmSMDBGCTL(LinkNum) … /* * LmSEQ CIO Bus Mode 3 Register. * Mode 3: Configuration and Setup, IOP Context SCB. */ #define LmM3SATATIMER(LinkNum) … #define LmM3INTVEC0(LinkNum) … #define LmM3INTVEC1(LinkNum) … #define LmM3INTVEC2(LinkNum) … #define LmM3INTVEC3(LinkNum) … #define LmM3INTVEC4(LinkNum) … #define LmM3INTVEC5(LinkNum) … #define LmM3INTVEC6(LinkNum) … #define LmM3INTVEC7(LinkNum) … #define LmM3INTVEC8(LinkNum) … #define LmM3INTVEC9(LinkNum) … #define LmM3INTVEC10(LinkNum) … #define LmM3FRMGAP(LinkNum) … #define LmBITL_TIMER(LinkNum) … #define LmWWN(LinkNum) … /* * LmSEQ CIO Bus Mode 5 Registers. * Mode 5: Phy/OOB Control and Status. */ #define LmSEQ_OOB_REG(phy_id, reg) … #define OOB_BFLTR … #define BFLTR_THR_MASK … #define BFLTR_TC_MASK … #define OOB_INIT_MIN … #define OOB_INIT_MAX … #define OOB_INIT_NEG … #define OOB_SAS_MIN … #define OOB_SAS_MAX … #define OOB_SAS_NEG … #define OOB_WAKE_MIN … #define OOB_WAKE_MAX … #define OOB_WAKE_NEG … #define OOB_IDLE_MAX … #define OOB_BURST_MAX … #define OOB_DATA_KBITS … #define OOB_ALIGN_0_DATA … #define OOB_ALIGN_1_DATA … #define D10_2_DATA_k … #define SYNC_DATA_k … #define ALIGN_1_DATA_k … #define ALIGN_0_DATA_k … #define BURST_DATA_k … #define OOB_PHY_RESET_COUNT … #define OOB_SIG_GEN … #define START_OOB … #define START_DWS … #define ALIGN_CNT3 … #define ALIGN_CNT2 … #define ALIGN_CNT1 … #define ALIGN_CNT4 … #define STOP_DWS … #define SEND_COMSAS … #define SEND_COMINIT … #define SEND_COMWAKE … #define OOB_XMIT … #define TX_ENABLE … #define XMIT_OOB_BURST … #define XMIT_D10_2 … #define XMIT_SYNC … #define XMIT_ALIGN_1 … #define XMIT_ALIGN_0 … #define FUNCTION_MASK … #define SAS_MODE_DIS … #define SATA_MODE_DIS … #define SPINUP_HOLD_DIS … #define HOT_PLUG_DIS … #define SATA_PS_DIS … #define FUNCTION_MASK_DEFAULT … #define OOB_MODE … #define SAS_MODE … #define SATA_MODE … #define SLOW_CLK … #define FORCE_XMIT_15 … #define PHY_SPEED_60 … #define PHY_SPEED_30 … #define PHY_SPEED_15 … #define CURRENT_STATUS … #define CURRENT_OOB_DONE … #define CURRENT_LOSS_OF_SIGNAL … #define CURRENT_SPINUP_HOLD … #define CURRENT_HOT_PLUG_CNCT … #define CURRENT_GTO_TIMEOUT … #define CURRENT_OOB_TIMEOUT … #define CURRENT_DEVICE_PRESENT … #define CURRENT_OOB_ERROR … #define CURRENT_OOB1_ERROR … #define CURRENT_OOB2_ERROR … #define DEVICE_ADDED_W_CNT … #define DEVICE_ADDED_WO_CNT … #define DEVICE_REMOVED … #define CURRENT_PHY_MASK … #define CURRENT_ERR_MASK … #define SPEED_MASK … #define SATA_SPEED_30_DIS … #define SATA_SPEED_15_DIS … #define SAS_SPEED_60_DIS … #define SAS_SPEED_30_DIS … #define SAS_SPEED_15_DIS … #define SAS_SPEED_MASK_DEFAULT … #define OOB_TIMER_ENABLE … #define HOT_PLUG_EN … #define RCD_EN … #define COMTIMER_EN … #define SNTT_EN … #define SNLT_EN … #define SNWT_EN … #define ALIGN_EN … #define OOB_STATUS … #define OOB_DONE … #define LOSS_OF_SIGNAL … #define SPINUP_HOLD … #define HOT_PLUG_CNCT … #define GTO_TIMEOUT … #define OOB_TIMEOUT … #define DEVICE_PRESENT … #define OOB_ERROR … #define OOB_STATUS_ERROR_MASK … #define OOB_STATUS_CLEAR … #define OOB_DONE_CLR … #define LOSS_OF_SIGNAL_CLR … #define SPINUP_HOLD_CLR … #define HOT_PLUG_CNCT_CLR … #define GTO_TIMEOUT_CLR … #define OOB_TIMEOUT_CLR … #define OOB_ERROR_CLR … #define HOT_PLUG_DELAY … /* In 5 ms units. 20 = 100 ms. */ #define HOTPLUG_DELAY_TIMEOUT … #define INT_ENABLE_2 … #define OOB_DONE_EN … #define LOSS_OF_SIGNAL_EN … #define SPINUP_HOLD_EN … #define HOT_PLUG_CNCT_EN … #define GTO_TIMEOUT_EN … #define OOB_TIMEOUT_EN … #define DEVICE_PRESENT_EN … #define OOB_ERROR_EN … #define PHY_CONTROL_0 … #define PHY_LOWPWREN_TX … #define PHY_LOWPWREN_RX … #define SPARE_REG_160_B5 … #define OFFSET_CANCEL_RX … /* bits 3:2 */ #define PHY_RXCOMCENTER_60V … #define PHY_RXCOMCENTER_70V … #define PHY_RXCOMCENTER_80V … #define PHY_RXCOMCENTER_90V … #define PHY_RXCOMCENTER_MASK … #define PHY_RESET … #define SAS_DEFAULT_SEL … #define PHY_CONTROL_1 … /* bits 2:0 */ #define SATA_PHY_DETLEVEL_50mv … #define SATA_PHY_DETLEVEL_75mv … #define SATA_PHY_DETLEVEL_100mv … #define SATA_PHY_DETLEVEL_125mv … #define SATA_PHY_DETLEVEL_150mv … #define SATA_PHY_DETLEVEL_175mv … #define SATA_PHY_DETLEVEL_200mv … #define SATA_PHY_DETLEVEL_225mv … #define SATA_PHY_DETLEVEL_MASK … /* bits 5:3 */ #define SAS_PHY_DETLEVEL_50mv … #define SAS_PHY_DETLEVEL_75mv … #define SAS_PHY_DETLEVEL_100mv … #define SAS_PHY_DETLEVEL_125mv … #define SAS_PHY_DETLEVEL_150mv … #define SAS_PHY_DETLEVEL_175mv … #define SAS_PHY_DETLEVEL_200mv … #define SAS_PHY_DETLEVEL_225mv … #define SAS_PHY_DETLEVEL_MASK … #define PHY_CONTROL_2 … /* bits 7:5 */ #define SATA_PHY_DRV_400mv … #define SATA_PHY_DRV_450mv … #define SATA_PHY_DRV_500mv … #define SATA_PHY_DRV_550mv … #define SATA_PHY_DRV_600mv … #define SATA_PHY_DRV_650mv … #define SATA_PHY_DRV_725mv … #define SATA_PHY_DRV_800mv … #define SATA_PHY_DRV_MASK … /* bits 4:3 */ #define SATA_PREEMP_0 … #define SATA_PREEMP_1 … #define SATA_PREEMP_2 … #define SATA_PREEMP_3 … #define SATA_PREEMP_MASK … #define SATA_CMSH1P5 … /* bits 1:0 */ #define SATA_SLEW_0 … #define SATA_SLEW_1 … #define SATA_SLEW_2 … #define SATA_SLEW_3 … #define SATA_SLEW_MASK … #define PHY_CONTROL_3 … /* bits 7:5 */ #define SAS_PHY_DRV_400mv … #define SAS_PHY_DRV_450mv … #define SAS_PHY_DRV_500mv … #define SAS_PHY_DRV_550mv … #define SAS_PHY_DRV_600mv … #define SAS_PHY_DRV_650mv … #define SAS_PHY_DRV_725mv … #define SAS_PHY_DRV_800mv … #define SAS_PHY_DRV_MASK … /* bits 4:3 */ #define SAS_PREEMP_0 … #define SAS_PREEMP_1 … #define SAS_PREEMP_2 … #define SAS_PREEMP_3 … #define SAS_PREEMP_MASK … #define SAS_CMSH1P5 … /* bits 1:0 */ #define SAS_SLEW_0 … #define SAS_SLEW_1 … #define SAS_SLEW_2 … #define SAS_SLEW_3 … #define SAS_SLEW_MASK … #define PHY_CONTROL_4 … #define PHY_DONE_CAL_TX … #define PHY_DONE_CAL_RX … #define RX_TERM_LOAD_DIS … #define TX_TERM_LOAD_DIS … #define AUTO_TERM_CAL_DIS … #define PHY_SIGDET_FLTR_EN … #define OSC_FREQ … #define PHY_START_CAL … /* * HST_PCIX2 Registers, Address Range: (0x00-0xFC) */ #define PCIX_REG_BASE_ADR … #define PCIC_VENDOR_ID … #define PCIC_DEVICE_ID … #define PCIC_COMMAND … #define INT_DIS … #define FBB_EN … #define SERR_EN … #define STEP_EN … #define PERR_EN … #define VGA_EN … #define MWI_EN … #define SPC_EN … #define MST_EN … #define MEM_EN … #define IO_EN … #define PCIC_STATUS … #define PERR_DET … #define SERR_GEN … #define MABT_DET … #define TABT_DET … #define TABT_GEN … #define DPERR_DET … #define CAP_LIST … #define INT_STAT … #define PCIC_DEVREV_ID … #define PCIC_CLASS_CODE … #define PCIC_CACHELINE_SIZE … #define PCIC_MBAR0 … #define PCIC_MBAR0_OFFSET … #define PCIC_MBAR1 … #define PCIC_MBAR1_OFFSET … #define PCIC_IOBAR … #define PCIC_IOBAR_OFFSET … #define PCIC_SUBVENDOR_ID … #define PCIC_SUBSYTEM_ID … #define PCIX_STATUS … #define RCV_SCE … #define UNEXP_SC … #define SC_DISCARD … #define ECC_CTRL_STAT … #define UNCOR_ECCERR … #define PCIC_PM_CSR … #define PWR_STATE_D0 … #define PWR_STATE_D1 … #define PWR_STATE_D2 … #define PWR_STATE_D3 … #define PCIC_BASE1 … #define BASE1_RSVD … #define PCIC_BASEA … #define BASEA_RSVD … #define BASEA_START … #define PCIC_BASEB … #define BASEB_RSVD … #define BASEB_IOMAP_MASK … #define BASEB_START … #define PCIC_BASEC … #define BASEC_RSVD … #define BASEC_MASK … #define BASEC_START … #define PCIC_MBAR_KEY … #define MBAR_KEY_MASK … #define PCIC_HSTPCIX_CNTRL … #define REWIND_DIS … #define SC_TMR_DIS … #define PCIC_MBAR0_MASK … #define PCIC_MBAR0_SIZE_MASK … #define PCIC_MBAR0_SIZE_SHIFT … #define PCIC_MBAR0_SIZE(val) … #define PCIC_FLASH_MBAR … #define PCIC_INTRPT_STAT … #define PCIC_TP_CTRL … /* * EXSI Registers, Address Range: (0x00-0xFC) */ #define EXSI_REG_BASE_ADR … #define EXSICNFGR … #define OCMINITIALIZED … #define ASIEN … #define HCMODE … #define PCIDEF … #define COMSTOCK … #define SEEPROMEND … #define MSTTIMEN … #define XREGEX … #define NVRAMW … #define NVRAMEX … #define SRAMW … #define SRAMEX … #define FLASHW … #define FLASHEX … #define SEEPROMCFG … #define SEEPROMTYP … #define SEEPROMEX … #define EXSICNTRLR … #define MODINT_EN … #define PMSTATR … #define FLASHRST … #define FLASHRDY … #define FLCNFGR … #define FLWEH_MASK … #define FLWESU_MASK … #define FLWEPW_MASK … #define FLOEH_MASK … #define FLOESU_MASK … #define FLOEPW_MASK … #define FLCSH_MASK … #define FLCSSU_MASK … #define FLCSPW_MASK … #define SRCNFGR … #define SRWEH_MASK … #define SRWESU_MASK … #define SRWEPW_MASK … #define SROEH_MASK … #define SROESU_MASK … #define SROEPW_MASK … #define SRCSH_MASK … #define SRCSSU_MASK … #define SRCSPW_MASK … #define NVCNFGR … #define NVWEH_MASK … #define NVWESU_MASK … #define NVWEPW_MASK … #define NVOEH_MASK … #define NVOESU_MASK … #define NVOEPW_MASK … #define NVCSH_MASK … #define NVCSSU_MASK … #define NVCSPW_MASK … #define XRCNFGR … #define XRWEH_MASK … #define XRWESU_MASK … #define XRWEPW_MASK … #define XROEH_MASK … #define XROESU_MASK … #define XROEPW_MASK … #define XRCSH_MASK … #define XRCSSU_MASK … #define XRCSPW_MASK … #define XREGADDR … #define XRADDRINCEN … #define XREGADD_MASK … #define XREGDATAR … #define XREGDATA_MASK … #define GPIOOER … #define GPIOODENR … #define GPIOINVR … #define GPIODATAOR … #define GPIODATAIR … #define GPIOCNFGR … #define GPIO_EXTSRC … #define SCNTRLR … #define SXFERDONE … #define SXFERCNT_MASK … #define SCMDTYP_MASK … #define SXFERSTART … #define SXFEREN … #define SRATER … #define SADDRR … #define SADDR_MASK … #define SDATAOR … #define SDATAOR0 … #define SDATAOR1 … #define SDATAOR2 … #define SDATAOR3 … #define SDATAIR … #define SDATAIR0 … #define SDATAIR1 … #define SDATAIR2 … #define SDATAIR3 … #define ASISTAT0R … #define ASIFMTERR … #define ASISEECHKERR … #define ASIERR … #define ASISTAT1R … #define CHECKSUM_MASK … #define ASIERRADDR … #define ASIERRDATAR … #define ASIERRSTATR … #define CPI2ASIBYTECNT_MASK … #define CPI2ASIBYTEEN_MASK … #define CPI2ASITARGERR_MASK … #define CPI2ASITARGMID_MASK … #define CPI2ASIMSTERR_MASK … /* * XSRAM, External SRAM (DWord and any BE pattern accessible) */ #define XSRAM_REG_BASE_ADDR … #define XSRAM_SIZE … /* * NVRAM Registers, Address Range: (0x00000 - 0x3FFFF). */ #define NVRAM_REG_BASE_ADR … #define NVRAM_MAX_BASE_ADR … /* OCM base address */ #define OCM_BASE_ADDR … #define OCM_MAX_SIZE … /* * Sequencers (Central and Link) Scratch RAM page definitions. */ /* * The Central Management Sequencer (CSEQ) Scratch Memory is a 1024 * byte memory. It is dword accessible and has byte parity * protection. The CSEQ accesses it in 32 byte windows, either as mode * dependent or mode independent memory. Each mode has 96 bytes, * (three 32 byte pages 0-2, not contiguous), leaving 128 bytes of * Mode Independent memory (four 32 byte pages 3-7). Note that mode * dependent scratch memory, Mode 8, page 0-3 overlaps mode * independent scratch memory, pages 0-3. * - 896 bytes of mode dependent scratch, 96 bytes per Modes 0-7, and * 128 bytes in mode 8, * - 259 bytes of mode independent scratch, common to modes 0-15. * * Sequencer scratch RAM is 1024 bytes. This scratch memory is * divided into mode dependent and mode independent scratch with this * memory further subdivided into pages of size 32 bytes. There are 5 * pages (160 bytes) of mode independent scratch and 3 pages of * dependent scratch memory for modes 0-7 (768 bytes). Mode 8 pages * 0-2 dependent scratch overlap with pages 0-2 of mode independent * scratch memory. * * The host accesses this scratch in a different manner from the * central sequencer. The sequencer has to use CSEQ registers CSCRPAGE * and CMnSCRPAGE to access the scratch memory. A flat mapping of the * scratch memory is available for software convenience and to prevent * corruption while the sequencer is running. This memory is mapped * onto addresses 800h - BFFh, total of 400h bytes. * * These addresses are mapped as follows: * * 800h-83Fh Mode Dependent Scratch Mode 0 Pages 0-1 * 840h-87Fh Mode Dependent Scratch Mode 1 Pages 0-1 * 880h-8BFh Mode Dependent Scratch Mode 2 Pages 0-1 * 8C0h-8FFh Mode Dependent Scratch Mode 3 Pages 0-1 * 900h-93Fh Mode Dependent Scratch Mode 4 Pages 0-1 * 940h-97Fh Mode Dependent Scratch Mode 5 Pages 0-1 * 980h-9BFh Mode Dependent Scratch Mode 6 Pages 0-1 * 9C0h-9FFh Mode Dependent Scratch Mode 7 Pages 0-1 * A00h-A5Fh Mode Dependent Scratch Mode 8 Pages 0-2 * Mode Independent Scratch Pages 0-2 * A60h-A7Fh Mode Dependent Scratch Mode 8 Page 3 * Mode Independent Scratch Page 3 * A80h-AFFh Mode Independent Scratch Pages 4-7 * B00h-B1Fh Mode Dependent Scratch Mode 0 Page 2 * B20h-B3Fh Mode Dependent Scratch Mode 1 Page 2 * B40h-B5Fh Mode Dependent Scratch Mode 2 Page 2 * B60h-B7Fh Mode Dependent Scratch Mode 3 Page 2 * B80h-B9Fh Mode Dependent Scratch Mode 4 Page 2 * BA0h-BBFh Mode Dependent Scratch Mode 5 Page 2 * BC0h-BDFh Mode Dependent Scratch Mode 6 Page 2 * BE0h-BFFh Mode Dependent Scratch Mode 7 Page 2 */ /* General macros */ #define CSEQ_PAGE_SIZE … /* All macros start with offsets from base + 0x800 (CMAPPEDSCR). * Mode dependent scratch page 0, mode 0. * For modes 1-7 you have to do arithmetic. */ #define CSEQ_LRM_SAVE_SINDEX … #define CSEQ_LRM_SAVE_SCBPTR … #define CSEQ_Q_LINK_HEAD … #define CSEQ_Q_LINK_TAIL … #define CSEQ_LRM_SAVE_SCRPAGE … /* Mode dependent scratch page 0 mode 8 macros. */ #define CSEQ_RET_ADDR … #define CSEQ_RET_SCBPTR … #define CSEQ_SAVE_SCBPTR … #define CSEQ_EMPTY_TRANS_CTX … #define CSEQ_RESP_LEN … #define CSEQ_TMF_SCBPTR … #define CSEQ_GLOBAL_PREV_SCB … #define CSEQ_GLOBAL_HEAD … #define CSEQ_CLEAR_LU_HEAD … #define CSEQ_TMF_OPCODE … #define CSEQ_SCRATCH_FLAGS … #define CSEQ_HSB_SITE … #define CSEQ_FIRST_INV_SCB_SITE … #define CSEQ_FIRST_INV_DDB_SITE … /* Mode dependent scratch page 1 mode 8 macros. */ #define CSEQ_LUN_TO_CLEAR … #define CSEQ_LUN_TO_CHECK … /* Mode dependent scratch page 2 mode 8 macros */ #define CSEQ_HQ_NEW_POINTER … #define CSEQ_HQ_DONE_BASE … #define CSEQ_HQ_DONE_POINTER … #define CSEQ_HQ_DONE_PASS … /* Mode independent scratch page 4 macros. */ #define CSEQ_Q_EXE_HEAD … #define CSEQ_Q_EXE_TAIL … #define CSEQ_Q_DONE_HEAD … #define CSEQ_Q_DONE_TAIL … #define CSEQ_Q_SEND_HEAD … #define CSEQ_Q_SEND_TAIL … #define CSEQ_Q_DMA2CHIM_HEAD … #define CSEQ_Q_DMA2CHIM_TAIL … #define CSEQ_Q_COPY_HEAD … #define CSEQ_Q_COPY_TAIL … #define CSEQ_REG0 … #define CSEQ_REG1 … #define CSEQ_REG2 … #define CSEQ_LINK_CTL_Q_MAP … #define CSEQ_MAX_CSEQ_MODE … #define CSEQ_FREE_LIST_HACK_COUNT … /* Mode independent scratch page 5 macros. */ #define CSEQ_EST_NEXUS_REQ_QUEUE … #define CSEQ_EST_NEXUS_REQ_COUNT … #define CSEQ_Q_EST_NEXUS_HEAD … #define CSEQ_Q_EST_NEXUS_TAIL … #define CSEQ_NEED_EST_NEXUS_SCB … #define CSEQ_EST_NEXUS_REQ_HEAD … #define CSEQ_EST_NEXUS_REQ_TAIL … #define CSEQ_EST_NEXUS_SCB_OFFSET … /* Mode independent scratch page 6 macros. */ #define CSEQ_INT_ROUT_RET_ADDR0 … #define CSEQ_INT_ROUT_RET_ADDR1 … #define CSEQ_INT_ROUT_SCBPTR … #define CSEQ_INT_ROUT_MODE … #define CSEQ_ISR_SCRATCH_FLAGS … #define CSEQ_ISR_SAVE_SINDEX … #define CSEQ_ISR_SAVE_DINDEX … #define CSEQ_Q_MONIRTT_HEAD … #define CSEQ_Q_MONIRTT_TAIL … #define CSEQ_FREE_SCB_MASK … #define CSEQ_BUILTIN_FREE_SCB_HEAD … #define CSEQ_BUILTIN_FREE_SCB_TAIL … #define CSEQ_EXTENDED_FREE_SCB_HEAD … #define CSEQ_EXTENDED_FREE_SCB_TAIL … /* Mode independent scratch page 7 macros. */ #define CSEQ_EMPTY_REQ_QUEUE … #define CSEQ_EMPTY_REQ_COUNT … #define CSEQ_Q_EMPTY_HEAD … #define CSEQ_Q_EMPTY_TAIL … #define CSEQ_NEED_EMPTY_SCB … #define CSEQ_EMPTY_REQ_HEAD … #define CSEQ_EMPTY_REQ_TAIL … #define CSEQ_EMPTY_SCB_OFFSET … #define CSEQ_PRIMITIVE_DATA … #define CSEQ_TIMEOUT_CONST … /*************************************************************************** * Link m Sequencer scratch RAM is 512 bytes. * This scratch memory is divided into mode dependent and mode * independent scratch with this memory further subdivided into * pages of size 32 bytes. There are 4 pages (128 bytes) of * mode independent scratch and 4 pages of dependent scratch * memory for modes 0-2 (384 bytes). * * The host accesses this scratch in a different manner from the * link sequencer. The sequencer has to use LSEQ registers * LmSCRPAGE and LmMnSCRPAGE to access the scratch memory. A flat * mapping of the scratch memory is available for software * convenience and to prevent corruption while the sequencer is * running. This memory is mapped onto addresses 800h - 9FFh. * * These addresses are mapped as follows: * * 800h-85Fh Mode Dependent Scratch Mode 0 Pages 0-2 * 860h-87Fh Mode Dependent Scratch Mode 0 Page 3 * Mode Dependent Scratch Mode 5 Page 0 * 880h-8DFh Mode Dependent Scratch Mode 1 Pages 0-2 * 8E0h-8FFh Mode Dependent Scratch Mode 1 Page 3 * Mode Dependent Scratch Mode 5 Page 1 * 900h-95Fh Mode Dependent Scratch Mode 2 Pages 0-2 * 960h-97Fh Mode Dependent Scratch Mode 2 Page 3 * Mode Dependent Scratch Mode 5 Page 2 * 980h-9DFh Mode Independent Scratch Pages 0-3 * 9E0h-9FFh Mode Independent Scratch Page 3 * Mode Dependent Scratch Mode 5 Page 3 * ****************************************************************************/ /* General macros */ #define LSEQ_MODE_SCRATCH_SIZE … #define LSEQ_PAGE_SIZE … #define LSEQ_MODE5_PAGE0_OFFSET … /* Common mode dependent scratch page 0 macros for modes 0,1,2, and 5 */ /* Indexed using LSEQ_MODE_SCRATCH_SIZE * mode, for modes 0,1,2. */ #define LmSEQ_RET_ADDR(LinkNum) … #define LmSEQ_REG0_MODE(LinkNum) … #define LmSEQ_MODE_FLAGS(LinkNum) … /* Mode flag macros (byte 0) */ #define SAS_SAVECTX_OCCURRED … #define SAS_OOBSVC_OCCURRED … #define SAS_OOB_DEVICE_PRESENT … #define SAS_CFGHDR_OCCURRED … #define SAS_RCV_INTS_ARE_DISABLED … #define SAS_OOB_HOT_PLUG_CNCT … #define SAS_AWAIT_OPEN_CONNECTION … #define SAS_CFGCMPLT_OCCURRED … /* Mode flag macros (byte 1) */ #define SAS_RLSSCB_OCCURRED … #define SAS_FORCED_HEADER_MISS … #define LmSEQ_RET_ADDR2(LinkNum) … #define LmSEQ_RET_ADDR1(LinkNum) … #define LmSEQ_OPCODE_TO_CSEQ(LinkNum) … #define LmSEQ_DATA_TO_CSEQ(LinkNum) … /* Mode dependent scratch page 0 macros for mode 0 (non-common) */ /* Absolute offsets */ #define LmSEQ_FIRST_INV_DDB_SITE(LinkNum) … #define LmSEQ_EMPTY_TRANS_CTX(LinkNum) … #define LmSEQ_RESP_LEN(LinkNum) … #define LmSEQ_FIRST_INV_SCB_SITE(LinkNum) … #define LmSEQ_INTEN_SAVE(LinkNum) … #define LmSEQ_LINK_RST_FRM_LEN(LinkNum) … #define LmSEQ_LINK_RST_PROTOCOL(LinkNum) … #define LmSEQ_RESP_STATUS(LinkNum) … #define LmSEQ_LAST_LOADED_SGE(LinkNum) … #define LmSEQ_SAVE_SCBPTR(LinkNum) … /* Mode dependent scratch page 0 macros for mode 1 (non-common) */ /* Absolute offsets */ #define LmSEQ_Q_XMIT_HEAD(LinkNum) … #define LmSEQ_M1_EMPTY_TRANS_CTX(LinkNum) … #define LmSEQ_INI_CONN_TAG(LinkNum) … #define LmSEQ_FAILED_OPEN_STATUS(LinkNum) … #define LmSEQ_XMIT_REQUEST_TYPE(LinkNum) … #define LmSEQ_M1_RESP_STATUS(LinkNum) … #define LmSEQ_M1_LAST_LOADED_SGE(LinkNum) … #define LmSEQ_M1_SAVE_SCBPTR(LinkNum) … /* Mode dependent scratch page 0 macros for mode 2 (non-common) */ #define LmSEQ_PORT_COUNTER(LinkNum) … #define LmSEQ_PM_TABLE_PTR(LinkNum) … #define LmSEQ_SATA_INTERLOCK_TMR_SAVE(LinkNum) … #define LmSEQ_IP_BITL(LinkNum) … #define LmSEQ_COPY_SMP_CONN_TAG(LinkNum) … #define LmSEQ_P0M2_OFFS1AH(LinkNum) … /* Mode dependent scratch page 0 macros for modes 4/5 (non-common) */ /* Absolute offsets */ #define LmSEQ_SAVED_OOB_STATUS(LinkNum) … #define LmSEQ_SAVED_OOB_MODE(LinkNum) … #define LmSEQ_Q_LINK_HEAD(LinkNum) … #define LmSEQ_LINK_RST_ERR(LinkNum) … #define LmSEQ_SAVED_OOB_SIGNALS(LinkNum) … #define LmSEQ_SAS_RESET_MODE(LinkNum) … #define LmSEQ_LINK_RESET_RETRY_COUNT(LinkNum) … #define LmSEQ_NUM_LINK_RESET_RETRIES(LinkNum) … #define LmSEQ_OOB_INT_ENABLES(LinkNum) … #define LmSEQ_NOTIFY_TIMER_DOWN_COUNT(LinkNum) … #define LmSEQ_NOTIFY_TIMER_TIMEOUT(LinkNum) … #define LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(LinkNum) … /* Mode dependent scratch page 1, mode 0 and mode 1 */ #define LmSEQ_SG_LIST_PTR_ADDR0(LinkNum) … #define LmSEQ_SG_LIST_PTR_ADDR1(LinkNum) … #define LmSEQ_M1_SG_LIST_PTR_ADDR0(LinkNum) … #define LmSEQ_M1_SG_LIST_PTR_ADDR1(LinkNum) … /* Mode dependent scratch page 1 macros for mode 2 */ /* Absolute offsets */ #define LmSEQ_INVALID_DWORD_COUNT(LinkNum) … #define LmSEQ_DISPARITY_ERROR_COUNT(LinkNum) … #define LmSEQ_LOSS_OF_SYNC_COUNT(LinkNum) … /* Mode dependent scratch page 1 macros for mode 4/5 */ #define LmSEQ_FRAME_TYPE_MASK(LinkNum) … #define LmSEQ_HASHED_DEST_ADDR_MASK(LinkNum) … #define LmSEQ_HASHED_SRC_ADDR_MASK_PRINT(LinkNum) … #define LmSEQ_HASHED_SRC_ADDR_MASK(LinkNum) … #define LmSEQ_NUM_FILL_BYTES_MASK(LinkNum) … #define LmSEQ_TAG_MASK(LinkNum) … #define LmSEQ_TARGET_PORT_XFER_TAG(LinkNum) … #define LmSEQ_DATA_OFFSET(LinkNum) … /* Mode dependent scratch page 2 macros for mode 0 */ /* Absolute offsets */ #define LmSEQ_SMP_RCV_TIMER_TERM_TS(LinkNum) … #define LmSEQ_DEVICE_BITS(LinkNum) … #define LmSEQ_SDB_DDB(LinkNum) … #define LmSEQ_SDB_NUM_TAGS(LinkNum) … #define LmSEQ_SDB_CURR_TAG(LinkNum) … /* Mode dependent scratch page 2 macros for mode 1 */ /* Absolute offsets */ /* byte 0 bits 1-0 are domain select. */ #define LmSEQ_TX_ID_ADDR_FRAME(LinkNum) … #define LmSEQ_OPEN_TIMER_TERM_TS(LinkNum) … #define LmSEQ_SRST_AS_TIMER_TERM_TS(LinkNum) … #define LmSEQ_LAST_LOADED_SG_EL(LinkNum) … /* Mode dependent scratch page 2 macros for mode 2 */ /* Absolute offsets */ #define LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(LinkNum) … #define LmSEQ_CLOSE_TIMER_TERM_TS(LinkNum) … #define LmSEQ_BREAK_TIMER_TERM_TS(LinkNum) … #define LmSEQ_DWS_RESET_TIMER_TERM_TS(LinkNum) … #define LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(LinkNum) … #define LmSEQ_MCTL_TIMER_TERM_TS(LinkNum) … /* Mode dependent scratch page 2 macros for mode 5 */ #define LmSEQ_COMINIT_TIMER_TERM_TS(LinkNum) … #define LmSEQ_RCV_ID_TIMER_TERM_TS(LinkNum) … #define LmSEQ_RCV_FIS_TIMER_TERM_TS(LinkNum) … #define LmSEQ_DEV_PRES_TIMER_TERM_TS(LinkNum) … /* Mode dependent scratch page 3 macros for modes 0 and 1 */ /* None defined */ /* Mode dependent scratch page 3 macros for modes 2 and 5 */ /* None defined */ /* Mode Independent Scratch page 0 macros. */ #define LmSEQ_Q_TGTXFR_HEAD(LinkNum) … #define LmSEQ_Q_TGTXFR_TAIL(LinkNum) … #define LmSEQ_LINK_NUMBER(LinkNum) … #define LmSEQ_SCRATCH_FLAGS(LinkNum) … /* * Currently only bit 0, SAS_DWSAQD, is used. */ #define SAS_DWSAQD … #define LmSEQ_CONNECTION_STATE(LinkNum) … /* Connection states (byte 0) */ #define SAS_WE_OPENED_CS … #define SAS_DEVICE_OPENED_CS … #define SAS_WE_SENT_DONE_CS … #define SAS_DEVICE_SENT_DONE_CS … #define SAS_WE_SENT_CLOSE_CS … #define SAS_DEVICE_SENT_CLOSE_CS … #define SAS_WE_SENT_BREAK_CS … #define SAS_DEVICE_SENT_BREAK_CS … /* Connection states (byte 1) */ #define SAS_OPN_TIMEOUT_OR_OPN_RJCT_CS … #define SAS_AIP_RECEIVED_CS … #define SAS_CREDIT_TIMEOUT_OCCURRED_CS … #define SAS_ACKNAK_TIMEOUT_OCCURRED_CS … #define SAS_SMPRSP_TIMEOUT_OCCURRED_CS … #define SAS_DONE_TIMEOUT_OCCURRED_CS … /* Connection states (byte 2) */ #define SAS_SMP_RESPONSE_RECEIVED_CS … #define SAS_INTLK_TIMEOUT_OCCURRED_CS … #define SAS_DEVICE_SENT_DMAT_CS … #define SAS_DEVICE_SENT_SYNCSRST_CS … #define SAS_CLEARING_AFFILIATION_CS … #define SAS_RXTASK_ACTIVE_CS … #define SAS_TXTASK_ACTIVE_CS … /* Connection states (byte 3) */ #define SAS_PHY_LOSS_OF_SIGNAL_CS … #define SAS_DWS_TIMER_EXPIRED_CS … #define SAS_LINK_RESET_NOT_COMPLETE_CS … #define SAS_PHY_DISABLED_CS … #define SAS_LINK_CTL_TASK_ACTIVE_CS … #define SAS_PHY_EVENT_TASK_ACTIVE_CS … #define SAS_DEVICE_SENT_ID_FRAME_CS … #define SAS_DEVICE_SENT_REG_FIS_CS … #define SAS_DEVICE_SENT_HARD_RESET_CS … #define SAS_PHY_IS_DOWN_FLAGS … #define SAS_LINK_CTL_PHY_EVENT_FLAGS … #define LmSEQ_CONCTL(LinkNum) … #define LmSEQ_CONSTAT(LinkNum) … #define LmSEQ_CONNECTION_MODES(LinkNum) … #define LmSEQ_REG1_ISR(LinkNum) … #define LmSEQ_REG2_ISR(LinkNum) … #define LmSEQ_REG3_ISR(LinkNum) … #define LmSEQ_REG0_ISR(LinkNum) … /* Mode independent scratch page 1 macros. */ #define LmSEQ_EST_NEXUS_SCBPTR0(LinkNum) … #define LmSEQ_EST_NEXUS_SCBPTR1(LinkNum) … #define LmSEQ_EST_NEXUS_SCBPTR2(LinkNum) … #define LmSEQ_EST_NEXUS_SCBPTR3(LinkNum) … #define LmSEQ_EST_NEXUS_SCB_OPCODE0(LinkNum) … #define LmSEQ_EST_NEXUS_SCB_OPCODE1(LinkNum) … #define LmSEQ_EST_NEXUS_SCB_OPCODE2(LinkNum) … #define LmSEQ_EST_NEXUS_SCB_OPCODE3(LinkNum) … #define LmSEQ_EST_NEXUS_SCB_HEAD(LinkNum) … #define LmSEQ_EST_NEXUS_SCB_TAIL(LinkNum) … #define LmSEQ_EST_NEXUS_BUF_AVAIL(LinkNum) … #define LmSEQ_TIMEOUT_CONST(LinkNum) … #define LmSEQ_ISR_SAVE_SINDEX(LinkNum) … #define LmSEQ_ISR_SAVE_DINDEX(LinkNum) … /* Mode independent scratch page 2 macros. */ #define LmSEQ_EMPTY_SCB_PTR0(LinkNum) … #define LmSEQ_EMPTY_SCB_PTR1(LinkNum) … #define LmSEQ_EMPTY_SCB_PTR2(LinkNum) … #define LmSEQ_EMPTY_SCB_PTR3(LinkNum) … #define LmSEQ_EMPTY_SCB_OPCD0(LinkNum) … #define LmSEQ_EMPTY_SCB_OPCD1(LinkNum) … #define LmSEQ_EMPTY_SCB_OPCD2(LinkNum) … #define LmSEQ_EMPTY_SCB_OPCD3(LinkNum) … #define LmSEQ_EMPTY_SCB_HEAD(LinkNum) … #define LmSEQ_EMPTY_SCB_TAIL(LinkNum) … #define LmSEQ_EMPTY_BUFS_AVAIL(LinkNum) … #define LmSEQ_ATA_SCR_REGS(LinkNum) … /* Mode independent scratch page 3 macros. */ #define LmSEQ_DEV_PRES_TMR_TOUT_CONST(LinkNum) … #define LmSEQ_SATA_INTERLOCK_TIMEOUT(LinkNum) … #define LmSEQ_STP_SHUTDOWN_TIMEOUT(LinkNum) … #define LmSEQ_SRST_ASSERT_TIMEOUT(LinkNum) … #define LmSEQ_RCV_FIS_TIMEOUT(LinkNum) … #define LmSEQ_ONE_MILLISEC_TIMEOUT(LinkNum) … #define LmSEQ_TEN_MS_COMINIT_TIMEOUT(LinkNum) … #define LmSEQ_SMP_RCV_TIMEOUT(LinkNum) … #endif
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