/* * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver * * Copyright (c) 2008-2009 USI Co., Ltd. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions, and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * substantially similar to the "NO WARRANTY" disclaimer below * ("Disclaimer") and any redistribution must be conditioned upon * including a substantially similar Disclaimer requirement for further * binary redistribution. * 3. Neither the names of the above-listed copyright holders nor the names * of any contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGES. * */ #ifndef _PMC8001_REG_H_ #define _PMC8001_REG_H_ #include <linux/types.h> #include <scsi/libsas.h> /* for Request Opcode of IOMB */ #define OPC_INB_ECHO … #define OPC_INB_PHYSTART … #define OPC_INB_PHYSTOP … #define OPC_INB_SSPINIIOSTART … #define OPC_INB_SSPINITMSTART … /* 0x8 RESV IN SPCv */ #define OPC_INB_RSVD … #define OPC_INB_DEV_HANDLE_ACCEPT … #define OPC_INB_SSPTGTIOSTART … #define OPC_INB_SSPTGTRSPSTART … /* 0xC, 0xD, 0xE removed in SPCv */ #define OPC_INB_SSP_ABORT … #define OPC_INB_DEREG_DEV_HANDLE … #define OPC_INB_GET_DEV_HANDLE … #define OPC_INB_SMP_REQUEST … /* 0x13 SMP_RESPONSE is removed in SPCv */ #define OPC_INB_SMP_ABORT … /* 0x16 RESV IN SPCv */ #define OPC_INB_RSVD1 … #define OPC_INB_SATA_HOST_OPSTART … #define OPC_INB_SATA_ABORT … #define OPC_INB_LOCAL_PHY_CONTROL … /* 0x1A RESV IN SPCv */ #define OPC_INB_RSVD2 … #define OPC_INB_FW_FLASH_UPDATE … #define OPC_INB_GPIO … #define OPC_INB_SAS_DIAG_MODE_START_END … #define OPC_INB_SAS_DIAG_EXECUTE … /* 0x25 RESV IN SPCv */ #define OPC_INB_RSVD3 … #define OPC_INB_GET_TIME_STAMP … #define OPC_INB_PORT_CONTROL … #define OPC_INB_GET_NVMD_DATA … #define OPC_INB_SET_NVMD_DATA … #define OPC_INB_SET_DEVICE_STATE … #define OPC_INB_GET_DEVICE_STATE … #define OPC_INB_SET_DEV_INFO … /* 0x2D RESV IN SPCv */ #define OPC_INB_RSVD4 … #define OPC_INB_SGPIO_REGISTER … #define OPC_INB_PCIE_DIAG_EXEC … #define OPC_INB_SET_CONTROLLER_CONFIG … #define OPC_INB_GET_CONTROLLER_CONFIG … #define OPC_INB_REG_DEV … #define OPC_INB_SAS_HW_EVENT_ACK … #define OPC_INB_GET_DEVICE_INFO … #define OPC_INB_GET_PHY_PROFILE … #define OPC_INB_FLASH_OP_EXT … #define OPC_INB_SET_PHY_PROFILE … #define OPC_INB_KEK_MANAGEMENT … #define OPC_INB_DEK_MANAGEMENT … #define OPC_INB_SSP_INI_DIF_ENC_IO … #define OPC_INB_SATA_DIF_ENC_IO … /* for Response Opcode of IOMB */ #define OPC_OUB_ECHO … #define OPC_OUB_RSVD … #define OPC_OUB_SSP_COMP … #define OPC_OUB_SMP_COMP … #define OPC_OUB_LOCAL_PHY_CNTRL … #define OPC_OUB_RSVD1 … #define OPC_OUB_DEREG_DEV … #define OPC_OUB_GET_DEV_HANDLE … #define OPC_OUB_SATA_COMP … #define OPC_OUB_SATA_EVENT … #define OPC_OUB_SSP_EVENT … #define OPC_OUB_RSVD2 … /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/ #define OPC_OUB_SSP_RECV_EVENT … #define OPC_OUB_RSVD3 … #define OPC_OUB_FW_FLASH_UPDATE … #define OPC_OUB_GPIO_RESPONSE … #define OPC_OUB_GPIO_EVENT … #define OPC_OUB_GENERAL_EVENT … #define OPC_OUB_SSP_ABORT_RSP … #define OPC_OUB_SATA_ABORT_RSP … #define OPC_OUB_SAS_DIAG_MODE_START_END … #define OPC_OUB_SAS_DIAG_EXECUTE … #define OPC_OUB_GET_TIME_STAMP … #define OPC_OUB_RSVD4 … #define OPC_OUB_PORT_CONTROL … #define OPC_OUB_SKIP_ENTRY … #define OPC_OUB_SMP_ABORT_RSP … #define OPC_OUB_GET_NVMD_DATA … #define OPC_OUB_SET_NVMD_DATA … #define OPC_OUB_DEVICE_HANDLE_REMOVAL … #define OPC_OUB_SET_DEVICE_STATE … #define OPC_OUB_GET_DEVICE_STATE … #define OPC_OUB_SET_DEV_INFO … #define OPC_OUB_RSVD5 … #define OPC_OUB_HW_EVENT … #define OPC_OUB_DEV_HANDLE_ARRIV … #define OPC_OUB_THERM_HW_EVENT … #define OPC_OUB_SGPIO_RESP … #define OPC_OUB_PCIE_DIAG_EXECUTE … #define OPC_OUB_DEV_REGIST … #define OPC_OUB_SAS_HW_EVENT_ACK … #define OPC_OUB_GET_DEVICE_INFO … /* spcv specific commands */ #define OPC_OUB_PHY_START_RESP … #define OPC_OUB_PHY_STOP_RESP … #define OPC_OUB_SET_CONTROLLER_CONFIG … #define OPC_OUB_GET_CONTROLLER_CONFIG … #define OPC_OUB_GET_PHY_PROFILE … #define OPC_OUB_FLASH_OP_EXT … #define OPC_OUB_SET_PHY_PROFILE … #define OPC_OUB_KEK_MANAGEMENT_RESP … #define OPC_OUB_DEK_MANAGEMENT_RESP … #define OPC_OUB_SSP_COALESCED_COMP_RESP … /* for phy start*/ #define SSC_DISABLE_15 … #define SSC_DISABLE_30 … #define SSC_DISABLE_60 … #define SAS_ASE … #define SPINHOLD_DISABLE … #define SPINHOLD_ENABLE … #define LINKMODE_SAS … #define LINKMODE_DSATA … #define LINKMODE_AUTO … #define LINKRATE_15 … #define LINKRATE_30 … #define LINKRATE_60 … #define LINKRATE_120 … /*phy_stop*/ #define PHY_STOP_SUCCESS … #define PHY_STOP_ERR_DEVICE_ATTACHED … /* phy_profile */ #define SAS_PHY_ANALOG_SETTINGS_PAGE … #define PHY_DWORD_LENGTH … /* Thermal related */ #define THERMAL_ENABLE … #define THERMAL_LOG_ENABLE … #define THERMAL_PAGE_CODE_7H … #define THERMAL_PAGE_CODE_8H … #define LTEMPHIL … #define RTEMPHIL … /* Encryption info */ #define SCRATCH_PAD3_ENC_DISABLED … #define SCRATCH_PAD3_ENC_DIS_ERR … #define SCRATCH_PAD3_ENC_ENA_ERR … #define SCRATCH_PAD3_ENC_READY … #define SCRATCH_PAD3_ENC_MASK … #define SCRATCH_PAD3_XTS_ENABLED … #define SCRATCH_PAD3_SMA_ENABLED … #define SCRATCH_PAD3_SMB_ENABLED … #define SCRATCH_PAD3_SMF_ENABLED … #define SCRATCH_PAD3_SM_MASK … #define SCRATCH_PAD3_ERR_CODE … #define SEC_MODE_SMF … #define SEC_MODE_SMA … #define SEC_MODE_SMB … #define CIPHER_MODE_ECB … #define CIPHER_MODE_XTS … #define KEK_MGMT_SUBOP_KEYCARDUPDATE … /* SAS protocol timer configuration page */ #define SAS_PROTOCOL_TIMER_CONFIG_PAGE … #define STP_MCT_TMO … #define SSP_MCT_TMO … #define SAS_MAX_OPEN_TIME … #define SMP_MAX_CONN_TIMER … #define STP_FRM_TIMER … #define STP_IDLE_TIME … #define SAS_MFD … #define SAS_OPNRJT_RTRY_INTVL … #define SAS_DOPNRJT_RTRY_TMO … #define SAS_COPNRJT_RTRY_TMO … #define SPCV_DOORBELL_CLEAR_TIMEOUT … #define SPC_DOORBELL_CLEAR_TIMEOUT … /* Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second. Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128 is DOPNRJT_RTRY_TMO */ #define SAS_DOPNRJT_RTRY_THR … #define SAS_COPNRJT_RTRY_THR … #define SAS_MAX_AIP … #define IT_NEXUS_TIMEOUT … #define PORT_RECOVERY_TIMEOUT … /* Port recovery timeout, 10000 ms for PM8006 controller */ #define CHIP_8006_PORT_RECOVERY_TIMEOUT … #ifdef __LITTLE_ENDIAN_BITFIELD struct sas_identify_frame_local { … } __packed; #elif defined(__BIG_ENDIAN_BITFIELD) struct sas_identify_frame_local { /* Byte 0 */ u8 _un0:1; u8 dev_type:3; u8 frame_type:4; /* Byte 1 */ u8 _un1; /* Byte 2 */ union { struct { u8 _un247:4; u8 ssp_iport:1; u8 stp_iport:1; u8 smp_iport:1; u8 _un20:1; }; u8 initiator_bits; }; /* Byte 3 */ union { struct { u8 _un347:4; u8 ssp_tport:1; u8 stp_tport:1; u8 smp_tport:1; u8 _un30:1; }; u8 target_bits; }; /* Byte 4 - 11 */ u8 _un4_11[8]; /* Byte 12 - 19 */ u8 sas_addr[SAS_ADDR_SIZE]; /* Byte 20 */ u8 phy_id; u8 _un21_27[7]; } __packed; #else #error "Bitfield order not defined!" #endif struct mpi_msg_hdr { … } __attribute__((packed, aligned …)); /* * brief the data structure of PHY Start Command * use to describe enable the phy (128 bytes) */ struct phy_start_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of PHY Start Command * use to disable the phy (128 bytes) */ struct phy_stop_req { … } __attribute__((packed, aligned …)); /* set device bits fis - device to host */ struct set_dev_bits_fis { … } __attribute__ ((packed)); /* PIO setup FIS - device to host */ struct pio_setup_fis { … } __attribute__ ((packed)); /* * brief the data structure of SATA Completion Response * use to describe the sata task response (64 bytes) */ struct sata_completion_resp { … } __attribute__((packed, aligned …)); /* * brief the data structure of SAS HW Event Notification * use to alert the host about the hardware event(64 bytes) */ /* updated outbound struct for spcv */ struct hw_event_resp { … } __attribute__((packed, aligned …)); /* * brief the data structure for thermal event notification */ struct thermal_hw_event { … } __attribute__((packed, aligned …)); /* * brief the data structure of REGISTER DEVICE Command * use to describe MPI REGISTER DEVICE Command (64 bytes) */ struct reg_dev_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of DEREGISTER DEVICE Command * use to request spc to remove all internal resources associated * with the device id (64 bytes) */ struct dereg_dev_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of DEVICE_REGISTRATION Response * use to notify the completion of the device registration (64 bytes) */ struct dev_reg_resp { … } __attribute__((packed, aligned …)); /* * brief the data structure of Local PHY Control Command * use to issue PHY CONTROL to local phy (64 bytes) */ struct local_phy_ctl_req { … } __attribute__((packed, aligned …)); /** * brief the data structure of Local Phy Control Response * use to describe MPI Local Phy Control Response (64 bytes) */ struct local_phy_ctl_resp { … } __attribute__((packed, aligned …)); #define OP_BITS … #define ID_BITS … /* * brief the data structure of PORT Control Command * use to control port properties (64 bytes) */ struct port_ctl_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of HW Event Ack Command * use to acknowledge receive HW event (64 bytes) */ struct hw_event_ack_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of PHY_START Response Command * indicates the completion of PHY_START command (64 bytes) */ struct phy_start_resp { … } __attribute__((packed, aligned …)); /* * brief the data structure of PHY_STOP Response Command * indicates the completion of PHY_STOP command (64 bytes) */ struct phy_stop_resp { … } __attribute__((packed, aligned …)); /* * brief the data structure of SSP Completion Response * use to indicate a SSP Completion (n bytes) */ struct ssp_completion_resp { … } __attribute__((packed, aligned …)); #define SSP_RESCV_BIT … /* * brief the data structure of SATA EVNET response * use to indicate a SATA Completion (64 bytes) */ struct sata_event_resp { … } __attribute__((packed, aligned …)); /* * brief the data structure of SSP EVNET esponse * use to indicate a SSP Completion (64 bytes) */ struct ssp_event_resp { … } __attribute__((packed, aligned …)); /** * brief the data structure of General Event Notification Response * use to describe MPI General Event Notification Response (64 bytes) */ struct general_event_resp { … } __attribute__((packed, aligned …)); #define GENERAL_EVENT_PAYLOAD … #define OPCODE_BITS … /* * brief the data structure of SMP Request Command * use to describe MPI SMP REQUEST Command (64 bytes) */ struct smp_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of SMP Completion Response * use to describe MPI SMP Completion Response (64 bytes) */ struct smp_completion_resp { … } __attribute__((packed, aligned …)); /* *brief the data structure of SSP SMP SATA Abort Command * use to describe MPI SSP SMP & SATA Abort Command (64 bytes) */ struct task_abort_req { … } __attribute__((packed, aligned …)); /** * brief the data structure of SSP SATA SMP Abort Response * use to describe SSP SMP & SATA Abort Response ( 64 bytes) */ struct task_abort_resp { … } __attribute__((packed, aligned …)); /** * brief the data structure of SAS Diagnostic Start/End Command * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) */ struct sas_diag_start_end_req { … } __attribute__((packed, aligned …)); /** * brief the data structure of SAS Diagnostic Execute Command * use to describe MPI SAS Diagnostic Execute Command (64 bytes) */ struct sas_diag_execute_req { … } __attribute__((packed, aligned …)); #define SAS_DIAG_PARAM_BYTES … /* * brief the data structure of Set Device State Command * use to describe MPI Set Device State Command (64 bytes) */ struct set_dev_state_req { … } __attribute__((packed, aligned …)); /* * brief the data structure of SATA Start Command * use to describe MPI SATA IO Start Command (64 bytes) * Note: This structure is common for normal / encryption I/O */ struct sata_start_req { … } __attribute__((packed, aligned …)); /** * brief the data structure of SSP INI TM Start Command * use to describe MPI SSP INI TM Start Command (64 bytes) */ struct ssp_ini_tm_start_req { … } __attribute__((packed, aligned …)); struct ssp_info_unit { … } __attribute__((packed, aligned …)); /** * brief the data structure of SSP INI IO Start Command * use to describe MPI SSP INI IO Start Command (64 bytes) * Note: This structure is common for normal / encryption I/O */ struct ssp_ini_io_start_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND * use to initiate SSP I/O operation with optional DIF/ENC */ struct ssp_dif_enc_io_req { … } __attribute__((packed, aligned …)); /** * brief the data structure of Firmware download * use to describe MPI FW DOWNLOAD Command (64 bytes) */ struct fw_flash_Update_req { … } __attribute__((packed, aligned …)); #define FWFLASH_IOMB_RESERVED_LEN … /** * brief the data structure of FW_FLASH_UPDATE Response * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) * */ struct fw_flash_Update_resp { … } __attribute__((packed, aligned …)); /** * brief the data structure of Get NVM Data Command * use to get data from NVM in HBA(64 bytes) */ struct get_nvm_data_req { … } __attribute__((packed, aligned …)); struct set_nvm_data_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for SET CONTROLLER CONFIG COMMAND * use to modify controller configuration */ struct set_ctrl_cfg_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for GET CONTROLLER CONFIG COMMAND * use to get controller configuration page */ struct get_ctrl_cfg_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for KEK_MANAGEMENT COMMAND * use for KEK management */ struct kek_mgmt_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for DEK_MANAGEMENT COMMAND * use for DEK management */ struct dek_mgmt_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for SET PHY PROFILE COMMAND * use to retrive phy specific information */ struct set_phy_profile_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for GET PHY PROFILE COMMAND * use to retrive phy specific information */ struct get_phy_profile_req { … } __attribute__((packed, aligned …)); /** * brief the data structure for EXT FLASH PARTITION * use to manage ext flash partition */ struct ext_flash_partition_req { … } __attribute__((packed, aligned …)); #define TWI_DEVICE … #define C_SEEPROM … #define VPD_FLASH … #define AAP1_RDUMP … #define IOP_RDUMP … #define EXPAN_ROM … #define IPMode … #define NVMD_TYPE … #define NVMD_STAT … #define NVMD_LEN … /** * brief the data structure of Get NVMD Data Response * use to describe MPI Get NVMD Data Response (64 bytes) */ struct get_nvm_data_resp { … } __attribute__((packed, aligned …)); /** * brief the data structure of SAS Diagnostic Start/End Response * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) * */ struct sas_diag_start_end_resp { … } __attribute__((packed, aligned …)); /** * brief the data structure of SAS Diagnostic Execute Response * use to describe MPI SAS Diagnostic Execute Response (64 bytes) * */ struct sas_diag_execute_resp { … } __attribute__((packed, aligned …)); /** * brief the data structure of Set Device State Response * use to describe MPI Set Device State Response (64 bytes) * */ struct set_dev_state_resp { … } __attribute__((packed, aligned …)); /* new outbound structure for spcv - begins */ /** * brief the data structure for SET CONTROLLER CONFIG COMMAND * use to modify controller configuration */ struct set_ctrl_cfg_resp { … } __attribute__((packed, aligned …)); struct get_ctrl_cfg_resp { … } __attribute__((packed, aligned …)); struct kek_mgmt_resp { … } __attribute__((packed, aligned …)); struct dek_mgmt_resp { … } __attribute__((packed, aligned …)); struct get_phy_profile_resp { … } __attribute__((packed, aligned …)); struct flash_op_ext_resp { … } __attribute__((packed, aligned …)); struct set_phy_profile_resp { … } __attribute__((packed, aligned …)); struct ssp_coalesced_comp_resp { … } __attribute__((packed, aligned …)); /* new outbound structure for spcv - ends */ /* brief data structure for SAS protocol timer configuration page. * */ struct SASProtocolTimerConfig { … } __attribute__((packed, aligned …)); SASProtocolTimerConfig_t; #define NDS_BITS … #define PDS_BITS … /* * HW Events type */ #define HW_EVENT_RESET_START … #define HW_EVENT_CHIP_RESET_COMPLETE … #define HW_EVENT_PHY_STOP_STATUS … #define HW_EVENT_SAS_PHY_UP … #define HW_EVENT_SATA_PHY_UP … #define HW_EVENT_SATA_SPINUP_HOLD … #define HW_EVENT_PHY_DOWN … #define HW_EVENT_PORT_INVALID … #define HW_EVENT_BROADCAST_CHANGE … #define HW_EVENT_PHY_ERROR … #define HW_EVENT_BROADCAST_SES … #define HW_EVENT_INBOUND_CRC_ERROR … #define HW_EVENT_HARD_RESET_RECEIVED … #define HW_EVENT_MALFUNCTION … #define HW_EVENT_ID_FRAME_TIMEOUT … #define HW_EVENT_BROADCAST_EXP … #define HW_EVENT_PHY_START_STATUS … #define HW_EVENT_LINK_ERR_INVALID_DWORD … #define HW_EVENT_LINK_ERR_DISPARITY_ERROR … #define HW_EVENT_LINK_ERR_CODE_VIOLATION … #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH … #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED … #define HW_EVENT_PORT_RECOVERY_TIMER_TMO … #define HW_EVENT_PORT_RECOVER … #define HW_EVENT_PORT_RESET_TIMER_TMO … #define HW_EVENT_PORT_RESET_COMPLETE … #define EVENT_BROADCAST_ASYNCH_EVENT … /* port state */ #define PORT_NOT_ESTABLISHED … #define PORT_VALID … #define PORT_LOSTCOMM … #define PORT_IN_RESET … #define PORT_3RD_PARTY_RESET … #define PORT_INVALID … /* * SSP/SMP/SATA IO Completion Status values */ #define IO_SUCCESS … #define IO_ABORTED … #define IO_OVERFLOW … #define IO_UNDERFLOW … #define IO_FAILED … #define IO_ABORT_RESET … #define IO_NOT_VALID … #define IO_NO_DEVICE … #define IO_ILLEGAL_PARAMETER … #define IO_LINK_FAILURE … #define IO_PROG_ERROR … #define IO_EDC_IN_ERROR … #define IO_EDC_OUT_ERROR … #define IO_ERROR_HW_TIMEOUT … #define IO_XFER_ERROR_BREAK … #define IO_XFER_ERROR_PHY_NOT_READY … #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED … #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION … #define IO_OPEN_CNX_ERROR_BREAK … #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS … #define IO_OPEN_CNX_ERROR_BAD_DESTINATION … #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED … #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY … #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION … /* This error code 0x18 is not used on SPCv */ #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR … #define IO_XFER_ERROR_NAK_RECEIVED … #define IO_XFER_ERROR_ACK_NAK_TIMEOUT … #define IO_XFER_ERROR_PEER_ABORTED … #define IO_XFER_ERROR_RX_FRAME … #define IO_XFER_ERROR_DMA … #define IO_XFER_ERROR_CREDIT_TIMEOUT … #define IO_XFER_ERROR_SATA_LINK_TIMEOUT … #define IO_XFER_ERROR_SATA … /* This error code 0x22 is not used on SPCv */ #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST … #define IO_XFER_ERROR_REJECTED_NCQ_MODE … #define IO_XFER_ERROR_ABORTED_NCQ_MODE … #define IO_XFER_OPEN_RETRY_TIMEOUT … /* This error code 0x25 is not used on SPCv */ #define IO_XFER_SMP_RESP_CONNECTION_ERROR … #define IO_XFER_ERROR_UNEXPECTED_PHASE … #define IO_XFER_ERROR_XFER_RDY_OVERRUN … #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED … #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT … /* The following error code 0x31 and 0x32 are not using (obsolete) */ #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK … #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK … #define IO_XFER_ERROR_OFFSET_MISMATCH … #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN … #define IO_XFER_CMD_FRAME_ISSUED … #define IO_ERROR_INTERNAL_SMP_RESOURCE … #define IO_PORT_IN_RESET … #define IO_DS_NON_OPERATIONAL … #define IO_DS_IN_RECOVERY … #define IO_TM_TAG_NOT_FOUND … #define IO_XFER_PIO_SETUP_ERROR … #define IO_SSP_EXT_IU_ZERO_LEN_ERROR … #define IO_DS_IN_ERROR … #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY … #define IO_ABORT_IN_PROGRESS … #define IO_ABORT_DELAYED … #define IO_INVALID_LENGTH … /********** additional response event values *****************/ #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT … #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED … #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO … #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST … #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE … #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED … #define IO_DS_INVALID … #define IO_FATAL_ERROR … /* WARNING: the value is not contiguous from here */ #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR … #define IO_XFER_DMA_ACTIVATE_TIMEOUT … #define IO_XFER_ERROR_INTERNAL_CRC_ERROR … #define MPI_IO_RQE_BUSY_FULL … #define IO_XFER_ERR_EOB_DATA_OVERRUN … #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME … #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED … #define MPI_ERR_IO_RESOURCE_UNAVAILABLE … #define MPI_ERR_ATAPI_DEVICE_BUSY … #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS … /* * An encryption IO request failed due to DEK Key Tag mismatch. * The key tag supplied in the encryption IOMB does not match with * the Key Tag in the referenced DEK Entry. */ #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH … #define IO_XFR_ERROR_CIPHER_MODE_INVALID … /* * An encryption I/O request failed because the initial value (IV) * in the unwrapped DEK blob didn't match the IV used to unwrap it. */ #define IO_XFR_ERROR_DEK_IV_MISMATCH … /* An encryption I/O request failed due to an internal RAM ECC or * interface error while unwrapping the DEK. */ #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR … /* An encryption I/O request failed due to an internal RAM ECC or * interface error while unwrapping the DEK. */ #define IO_XFR_ERROR_INTERNAL_RAM … /* * An encryption I/O request failed * because the DEK index specified in the I/O was outside the bounds of * the total number of entries in the host DEK table. */ #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046 /* define DIF IO response error status code */ #define IO_XFR_ERROR_DIF_MISMATCH … #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH … #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH … #define IO_XFR_ERROR_DIF_CRC_MISMATCH … /* define operator management response status and error qualifier code */ #define OPR_MGMT_OP_NOT_SUPPORTED … #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL … #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND … #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH … #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED … #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL … #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE … /***************** additional response event values ***************/ /* WARNING: This error code must always be the last number. * If you add error code, modify this code also * It is used as an index */ #define IO_ERROR_UNKNOWN_GENERIC … /* MSGU CONFIGURATION TABLE*/ #define SPCv_MSGU_CFG_TABLE_UPDATE … #define SPCv_MSGU_CFG_TABLE_RESET … #define SPCv_MSGU_CFG_TABLE_FREEZE … #define SPCv_MSGU_CFG_TABLE_UNFREEZE … #define MSGU_IBDB_SET … #define MSGU_HOST_INT_STATUS … #define MSGU_HOST_INT_MASK … #define MSGU_IOPIB_INT_STATUS … #define MSGU_IOPIB_INT_MASK … #define MSGU_IBDB_CLEAR … #define MSGU_MSGU_CONTROL … #define MSGU_ODR … #define MSGU_ODCR … #define MSGU_ODMR … #define MSGU_ODMR_U … #define MSGU_ODMR_CLR … #define MSGU_ODMR_CLR_U … #define MSGU_OD_RSVD … #define MSGU_SCRATCH_PAD_0 … #define MSGU_SCRATCH_PAD_1 … #define MSGU_SCRATCH_PAD_2 … #define MSGU_SCRATCH_PAD_3 … #define MSGU_HOST_SCRATCH_PAD_0 … #define MSGU_HOST_SCRATCH_PAD_1 … #define MSGU_HOST_SCRATCH_PAD_2 … #define MSGU_HOST_SCRATCH_PAD_3 … #define MSGU_HOST_SCRATCH_PAD_4 … #define MSGU_HOST_SCRATCH_PAD_5 … #define MSGU_SCRATCH_PAD_RSVD_0 … #define MSGU_SCRATCH_PAD_RSVD_1 … #define MSGU_SCRATCHPAD1_RAAE_STATE_ERR(x) … #define MSGU_SCRATCHPAD1_ILA_STATE_ERR(x) … #define MSGU_SCRATCHPAD1_BOOTLDR_STATE_ERR(x) … #define MSGU_SCRATCHPAD1_IOP0_STATE_ERR(x) … #define MSGU_SCRATCHPAD1_IOP1_STATE_ERR(x) … #define MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(x) … /* bit definition for ODMR register */ #define ODMR_MASK_ALL … #define ODMR_CLEAR_ALL … /* bit definition for ODCR register */ #define ODCR_CLEAR_ALL … /* MSIX Interupts */ #define MSIX_TABLE_OFFSET … #define MSIX_TABLE_ELEMENT_SIZE … #define MSIX_INTERRUPT_CONTROL_OFFSET … #define MSIX_TABLE_BASE … #define MSIX_INTERRUPT_DISABLE … #define MSIX_INTERRUPT_ENABLE … /* state definition for Scratch Pad1 register */ #define SCRATCH_PAD_RAAE_READY … #define SCRATCH_PAD_ILA_READY … #define SCRATCH_PAD_BOOT_LOAD_SUCCESS … #define SCRATCH_PAD_IOP0_READY … #define SCRATCH_PAD_IOP1_READY … #define SCRATCH_PAD_MIPSALL_READY_16PORT … #define SCRATCH_PAD_MIPSALL_READY_8PORT … /* boot loader state */ #define SCRATCH_PAD1_BOOTSTATE_MASK … #define SCRATCH_PAD1_BOOTSTATE_SUCESS … #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM … #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP … #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET … #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR … #define SCRATCH_PAD1_BOOTSTATE_R1 … #define SCRATCH_PAD1_BOOTSTATE_R2 … #define SCRATCH_PAD1_BOOTSTATE_FATAL … /* state definition for Scratch Pad2 register */ #define SCRATCH_PAD2_POR … #define SCRATCH_PAD2_SFR … #define SCRATCH_PAD2_ERR … #define SCRATCH_PAD2_RDY … #define SCRATCH_PAD2_FWRDY_RST … #define SCRATCH_PAD2_IOPRDY_RST … #define SCRATCH_PAD2_STATE_MASK … #define SCRATCH_PAD2_RESERVED … #define SCRATCH_PAD_ERROR_MASK … #define SCRATCH_PAD_STATE_MASK … /*state definition for Scratchpad Rsvd 0, Offset 0x6C, Non-fatal*/ #define NON_FATAL_SPBC_LBUS_ECC_ERR … #define NON_FATAL_BDMA_ERR … #define NON_FATAL_THERM_OVERTEMP_ERR … /* main configuration offset - byte offset */ #define MAIN_SIGNATURE_OFFSET … #define MAIN_INTERFACE_REVISION … #define MAIN_FW_REVISION … #define MAIN_MAX_OUTSTANDING_IO_OFFSET … #define MAIN_MAX_SGL_OFFSET … #define MAIN_CNTRL_CAP_OFFSET … #define MAIN_GST_OFFSET … #define MAIN_IBQ_OFFSET … #define MAIN_OBQ_OFFSET … #define MAIN_IQNPPD_HPPD_OFFSET … /* 0x28 - 0x4C - RSVD */ #define MAIN_EVENT_CRC_CHECK … #define MAIN_EVENT_LOG_ADDR_HI … #define MAIN_EVENT_LOG_ADDR_LO … #define MAIN_EVENT_LOG_BUFF_SIZE … #define MAIN_EVENT_LOG_OPTION … #define MAIN_PCS_EVENT_LOG_ADDR_HI … #define MAIN_PCS_EVENT_LOG_ADDR_LO … #define MAIN_PCS_EVENT_LOG_BUFF_SIZE … #define MAIN_PCS_EVENT_LOG_OPTION … #define MAIN_FATAL_ERROR_INTERRUPT … #define MAIN_FATAL_ERROR_RDUMP0_OFFSET … #define MAIN_FATAL_ERROR_RDUMP0_LENGTH … #define MAIN_FATAL_ERROR_RDUMP1_OFFSET … #define MAIN_FATAL_ERROR_RDUMP1_LENGTH … #define MAIN_GPIO_LED_FLAGS_OFFSET … #define MAIN_ANALOG_SETUP_OFFSET … #define MAIN_INT_VECTOR_TABLE_OFFSET … #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET … #define MAIN_PORT_RECOVERY_TIMER … #define MAIN_INT_REASSERTION_DELAY … #define MAIN_MPI_ILA_RELEASE_TYPE … #define MAIN_MPI_INACTIVE_FW_VERSION … /* Gereral Status Table offset - byte offset */ #define GST_GSTLEN_MPIS_OFFSET … #define GST_IQ_FREEZE_STATE0_OFFSET … #define GST_IQ_FREEZE_STATE1_OFFSET … #define GST_MSGUTCNT_OFFSET … #define GST_IOPTCNT_OFFSET … /* 0x14 - 0x34 - RSVD */ #define GST_GPIO_INPUT_VAL … /* 0x3c - 0x40 - RSVD */ #define GST_RERRINFO_OFFSET0 … #define GST_RERRINFO_OFFSET1 … #define GST_RERRINFO_OFFSET2 … #define GST_RERRINFO_OFFSET3 … #define GST_RERRINFO_OFFSET4 … #define GST_RERRINFO_OFFSET5 … #define GST_RERRINFO_OFFSET6 … #define GST_RERRINFO_OFFSET7 … /* General Status Table - MPI state */ #define GST_MPI_STATE_UNINIT … #define GST_MPI_STATE_INIT … #define GST_MPI_STATE_TERMINATION … #define GST_MPI_STATE_ERROR … #define GST_MPI_STATE_MASK … /* Per SAS PHY Attributes */ #define PSPA_PHYSTATE0_OFFSET … #define PSPA_OB_HW_EVENT_PID0_OFFSET … #define PSPA_PHYSTATE1_OFFSET … #define PSPA_OB_HW_EVENT_PID1_OFFSET … #define PSPA_PHYSTATE2_OFFSET … #define PSPA_OB_HW_EVENT_PID2_OFFSET … #define PSPA_PHYSTATE3_OFFSET … #define PSPA_OB_HW_EVENT_PID3_OFFSET … #define PSPA_PHYSTATE4_OFFSET … #define PSPA_OB_HW_EVENT_PID4_OFFSET … #define PSPA_PHYSTATE5_OFFSET … #define PSPA_OB_HW_EVENT_PID5_OFFSET … #define PSPA_PHYSTATE6_OFFSET … #define PSPA_OB_HW_EVENT_PID6_OFFSET … #define PSPA_PHYSTATE7_OFFSET … #define PSPA_OB_HW_EVENT_PID7_OFFSET … #define PSPA_PHYSTATE8_OFFSET … #define PSPA_OB_HW_EVENT_PID8_OFFSET … #define PSPA_PHYSTATE9_OFFSET … #define PSPA_OB_HW_EVENT_PID9_OFFSET … #define PSPA_PHYSTATE10_OFFSET … #define PSPA_OB_HW_EVENT_PID10_OFFSET … #define PSPA_PHYSTATE11_OFFSET … #define PSPA_OB_HW_EVENT_PID11_OFFSET … #define PSPA_PHYSTATE12_OFFSET … #define PSPA_OB_HW_EVENT_PID12_OFFSET … #define PSPA_PHYSTATE13_OFFSET … #define PSPA_OB_HW_EVENT_PID13_OFFSET … #define PSPA_PHYSTATE14_OFFSET … #define PSPA_OB_HW_EVENT_PID14_OFFSET … #define PSPA_PHYSTATE15_OFFSET … #define PSPA_OB_HW_EVENT_PID15_OFFSET … /* end PSPA */ /* inbound queue configuration offset - byte offset */ #define IB_PROPERITY_OFFSET … #define IB_BASE_ADDR_HI_OFFSET … #define IB_BASE_ADDR_LO_OFFSET … #define IB_CI_BASE_ADDR_HI_OFFSET … #define IB_CI_BASE_ADDR_LO_OFFSET … #define IB_PIPCI_BAR … #define IB_PIPCI_BAR_OFFSET … #define IB_RESERVED_OFFSET … /* outbound queue configuration offset - byte offset */ #define OB_PROPERITY_OFFSET … #define OB_BASE_ADDR_HI_OFFSET … #define OB_BASE_ADDR_LO_OFFSET … #define OB_PI_BASE_ADDR_HI_OFFSET … #define OB_PI_BASE_ADDR_LO_OFFSET … #define OB_CIPCI_BAR … #define OB_CIPCI_BAR_OFFSET … #define OB_INTERRUPT_COALES_OFFSET … #define OB_DYNAMIC_COALES_OFFSET … #define OB_PROPERTY_INT_ENABLE … #define MBIC_NMI_ENABLE_VPE0_IOP … #define MBIC_NMI_ENABLE_VPE0_AAP1 … /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ #define PCIE_EVENT_INTERRUPT_ENABLE … #define PCIE_EVENT_INTERRUPT … #define PCIE_ERROR_INTERRUPT_ENABLE … #define PCIE_ERROR_INTERRUPT … /* SPCV soft reset */ #define SPC_REG_SOFT_RESET … #define SPCv_NORMAL_RESET_VALUE … #define SPCv_SOFT_RESET_READ_MASK … #define SPCv_SOFT_RESET_NO_RESET … #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED … #define SPCv_SOFT_RESET_HDA_MODE_OCCURED … #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED … /* signature definition for host scratch pad0 register */ #define SPC_SOFT_RESET_SIGNATURE … /* Signature for Soft Reset */ /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ #define SPC_REG_RESET … /* bit definition for SPC_RESET register */ #define SPC_REG_RESET_OSSP … #define SPC_REG_RESET_RAAE … #define SPC_REG_RESET_PCS_SPBC … #define SPC_REG_RESET_PCS_IOP_SS … #define SPC_REG_RESET_PCS_AAP1_SS … #define SPC_REG_RESET_PCS_AAP2_SS … #define SPC_REG_RESET_PCS_LM … #define SPC_REG_RESET_PCS … #define SPC_REG_RESET_GSM … #define SPC_REG_RESET_DDR2 … #define SPC_REG_RESET_BDMA_CORE … #define SPC_REG_RESET_BDMA_SXCBI … #define SPC_REG_RESET_PCIE_AL_SXCBI … #define SPC_REG_RESET_PCIE_PWR … #define SPC_REG_RESET_PCIE_SFT … #define SPC_REG_RESET_PCS_SXCBI … #define SPC_REG_RESET_LMS_SXCBI … #define SPC_REG_RESET_PMIC_SXCBI … #define SPC_REG_RESET_PMIC_CORE … #define SPC_REG_RESET_PCIE_PC_SXCBI … #define SPC_REG_RESET_DEVICE … /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ #define SPCV_IBW_AXI_TRANSLATION_LOW … #define MBIC_AAP1_ADDR_BASE … #define MBIC_IOP_ADDR_BASE … #define GSM_ADDR_BASE … /* Dynamic map through Bar4 - 0x00700000 */ #define GSM_CONFIG_RESET … #define RAM_ECC_DB_ERR … #define GSM_READ_ADDR_PARITY_INDIC … #define GSM_WRITE_ADDR_PARITY_INDIC … #define GSM_WRITE_DATA_PARITY_INDIC … #define GSM_READ_ADDR_PARITY_CHECK … #define GSM_WRITE_ADDR_PARITY_CHECK … #define GSM_WRITE_DATA_PARITY_CHECK … #define RB6_ACCESS_REG … #define HDAC_EXEC_CMD … #define HDA_C_PA … #define HDA_SEQ_ID_BITS … #define HDA_GSM_OFFSET_BITS … #define HDA_GSM_CMD_OFFSET_BITS … #define HDA_GSM_RSP_OFFSET_BITS … #define MBIC_AAP1_ADDR_BASE … #define MBIC_IOP_ADDR_BASE … #define GSM_ADDR_BASE … #define SPC_TOP_LEVEL_ADDR_BASE … #define GSM_CONFIG_RESET_VALUE … #define GPIO_ADDR_BASE … #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET … /* RB6 offset */ #define SPC_RB6_OFFSET … /* Magic number of soft reset for RB6 */ #define RB6_MAGIC_NUMBER_RST … /* Device Register status */ #define DEVREG_SUCCESS … #define DEVREG_FAILURE_OUT_OF_RESOURCE … #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED … #define DEVREG_FAILURE_INVALID_PHY_ID … #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED … #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE … #define DEVREG_FAILURE_PORT_NOT_VALID_STATE … #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID … #define MEMBASE_II_SHIFT_REGISTER … #endif /** * As we know sleep (1~20) ms may result in sleep longer than ~20 ms, hence we * choose 20 ms interval. */ #define FW_READY_INTERVAL …
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