// SPDX-License-Identifier: GPL-2.0-only /* * Aic94xx SAS/SATA driver dump interface. * * Copyright (C) 2004 Adaptec, Inc. All rights reserved. * Copyright (C) 2004 David Chaw <[email protected]> * Copyright (C) 2005 Luben Tuikov <[email protected]> * * 2005/07/14/LT Complete overhaul of this file. Update pages, register * locations, names, etc. Make use of macros. Print more information. * Print all cseq and lseq mip and mdp. */ #include <linux/pci.h> #include "aic94xx.h" #include "aic94xx_reg.h" #include "aic94xx_reg_def.h" #include "aic94xx_sas.h" #include "aic94xx_dump.h" #ifdef ASD_DEBUG #define MD(x) … #define MODE_COMMON … #define MODE_0_7 … static const struct lseq_cio_regs { … } LSEQmCIOREGS[] = …; /* static struct lseq_cio_regs LSEQmOOBREGS[] = { {"OOB_BFLTR" ,0x100, 8, MD(5)}, {"OOB_INIT_MIN" ,0x102,16, MD(5)}, {"OOB_INIT_MAX" ,0x104,16, MD(5)}, {"OOB_INIT_NEG" ,0x106,16, MD(5)}, {"OOB_SAS_MIN" ,0x108,16, MD(5)}, {"OOB_SAS_MAX" ,0x10A,16, MD(5)}, {"OOB_SAS_NEG" ,0x10C,16, MD(5)}, {"OOB_WAKE_MIN" ,0x10E,16, MD(5)}, {"OOB_WAKE_MAX" ,0x110,16, MD(5)}, {"OOB_WAKE_NEG" ,0x112,16, MD(5)}, {"OOB_IDLE_MAX" ,0x114,16, MD(5)}, {"OOB_BURST_MAX" ,0x116,16, MD(5)}, {"OOB_XMIT_BURST" ,0x118, 8, MD(5)}, {"OOB_SEND_PAIRS" ,0x119, 8, MD(5)}, {"OOB_INIT_IDLE" ,0x11A, 8, MD(5)}, {"OOB_INIT_NEGO" ,0x11C, 8, MD(5)}, {"OOB_SAS_IDLE" ,0x11E, 8, MD(5)}, {"OOB_SAS_NEGO" ,0x120, 8, MD(5)}, {"OOB_WAKE_IDLE" ,0x122, 8, MD(5)}, {"OOB_WAKE_NEGO" ,0x124, 8, MD(5)}, {"OOB_DATA_KBITS" ,0x126, 8, MD(5)}, {"OOB_BURST_DATA" ,0x128,32, MD(5)}, {"OOB_ALIGN_0_DATA" ,0x12C,32, MD(5)}, {"OOB_ALIGN_1_DATA" ,0x130,32, MD(5)}, {"OOB_SYNC_DATA" ,0x134,32, MD(5)}, {"OOB_D10_2_DATA" ,0x138,32, MD(5)}, {"OOB_PHY_RST_CNT" ,0x13C,32, MD(5)}, {"OOB_SIG_GEN" ,0x140, 8, MD(5)}, {"OOB_XMIT" ,0x141, 8, MD(5)}, {"FUNCTION_MAKS" ,0x142, 8, MD(5)}, {"OOB_MODE" ,0x143, 8, MD(5)}, {"CURRENT_STATUS" ,0x144, 8, MD(5)}, {"SPEED_MASK" ,0x145, 8, MD(5)}, {"PRIM_COUNT" ,0x146, 8, MD(5)}, {"OOB_SIGNALS" ,0x148, 8, MD(5)}, {"OOB_DATA_DET" ,0x149, 8, MD(5)}, {"OOB_TIME_OUT" ,0x14C, 8, MD(5)}, {"OOB_TIMER_ENABLE" ,0x14D, 8, MD(5)}, {"OOB_STATUS" ,0x14E, 8, MD(5)}, {"HOT_PLUG_DELAY" ,0x150, 8, MD(5)}, {"RCD_DELAY" ,0x151, 8, MD(5)}, {"COMSAS_TIMER" ,0x152, 8, MD(5)}, {"SNTT_DELAY" ,0x153, 8, MD(5)}, {"SPD_CHNG_DELAY" ,0x154, 8, MD(5)}, {"SNLT_DELAY" ,0x155, 8, MD(5)}, {"SNWT_DELAY" ,0x156, 8, MD(5)}, {"ALIGN_DELAY" ,0x157, 8, MD(5)}, {"INT_ENABLE_0" ,0x158, 8, MD(5)}, {"INT_ENABLE_1" ,0x159, 8, MD(5)}, {"INT_ENABLE_2" ,0x15A, 8, MD(5)}, {"INT_ENABLE_3" ,0x15B, 8, MD(5)}, {"OOB_TEST_REG" ,0x15C, 8, MD(5)}, {"PHY_CONTROL_0" ,0x160, 8, MD(5)}, {"PHY_CONTROL_1" ,0x161, 8, MD(5)}, {"PHY_CONTROL_2" ,0x162, 8, MD(5)}, {"PHY_CONTROL_3" ,0x163, 8, MD(5)}, {"PHY_OOB_CAL_TX" ,0x164, 8, MD(5)}, {"PHY_OOB_CAL_RX" ,0x165, 8, MD(5)}, {"OOB_PHY_CAL_TX" ,0x166, 8, MD(5)}, {"OOB_PHY_CAL_RX" ,0x167, 8, MD(5)}, {"PHY_CONTROL_4" ,0x168, 8, MD(5)}, {"PHY_TEST" ,0x169, 8, MD(5)}, {"PHY_PWR_CTL" ,0x16A, 8, MD(5)}, {"PHY_PWR_DELAY" ,0x16B, 8, MD(5)}, {"OOB_SM_CON" ,0x16C, 8, MD(5)}, {"ADDR_TRAP_1" ,0x16D, 8, MD(5)}, {"ADDR_NEXT_1" ,0x16E, 8, MD(5)}, {"NEXT_ST_1" ,0x16F, 8, MD(5)}, {"OOB_SM_STATE" ,0x170, 8, MD(5)}, {"ADDR_TRAP_2" ,0x171, 8, MD(5)}, {"ADDR_NEXT_2" ,0x172, 8, MD(5)}, {"NEXT_ST_2" ,0x173, 8, MD(5)}, {NULL, 0, 0, 0 } }; */ #define STR_8BIT … #define STR_16BIT … #define STR_32BIT … #define STR_64BIT … #define PRINT_REG_8bit(_ha, _n, _r) … #define PRINT_REG_16bit(_ha, _n, _r) … #define PRINT_REG_32bit(_ha, _n, _r) … #define PRINT_CREG_8bit(_ha, _n) … #define PRINT_CREG_16bit(_ha, _n) … #define PRINT_CREG_32bit(_ha, _n) … #define MSTR_8BIT … #define MSTR_16BIT … #define MSTR_32BIT … #define PRINT_MREG_8bit(_ha, _m, _n, _r) … #define PRINT_MREG_16bit(_ha, _m, _n, _r) … #define PRINT_MREG_32bit(_ha, _m, _n, _r) … /* can also be used for MD when the register is mode aware already */ #define PRINT_MIS_byte(_ha, _n) … #define PRINT_MIS_word(_ha, _n) … #define PRINT_MIS_dword(_ha, _n) … #define PRINT_MIS_qword(_ha, _n) … #define CMDP_REG(_n, _m) … #define PRINT_CMDP_word(_ha, _n) … #define PRINT_CMDP_byte(_ha, _n) … static void asd_dump_cseq_state(struct asd_ha_struct *asd_ha) { … } #define PRINT_LREG_8bit(_h, _lseq, _n) … #define PRINT_LREG_16bit(_h, _lseq, _n) … #define PRINT_LREG_32bit(_h, _lseq, _n) … #define PRINT_LMIP_byte(_h, _lseq, _n) … #define PRINT_LMIP_word(_h, _lseq, _n) … #define PRINT_LMIP_dword(_h, _lseq, _n) … #define PRINT_LMIP_qword(_h, _lseq, _n) … static void asd_print_lseq_cio_reg(struct asd_ha_struct *asd_ha, u32 lseq_cio_addr, int i) { … } static void asd_dump_lseq_state(struct asd_ha_struct *asd_ha, int lseq) { … } /** * asd_dump_seq_state -- dump CSEQ and LSEQ states * @asd_ha: pointer to host adapter structure * @lseq_mask: mask of LSEQs of interest */ void asd_dump_seq_state(struct asd_ha_struct *asd_ha, u8 lseq_mask) { … } void asd_dump_frame_rcvd(struct asd_phy *phy, struct done_list_struct *dl) { … } #endif /* ASD_DEBUG */
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