/* SPDX-License-Identifier: GPL-2.0-only */ /* * QLogic iSCSI HBA Driver * Copyright (c) 2003-2013 QLogic Corporation */ #ifndef _QLA4X_FW_H #define _QLA4X_FW_H #define MAX_PRST_DEV_DB_ENTRIES … #define MIN_DISC_DEV_DB_ENTRY … #define MAX_DEV_DB_ENTRIES … #define MAX_DEV_DB_ENTRIES_40XX … /************************************************************************* * * ISP 4010 I/O Register Set Structure and Definitions * *************************************************************************/ struct port_ctrl_stat_regs { … }; struct host_mem_cfg_regs { … }; /* * ISP 82xx I/O Register Set structure definitions. */ struct device_reg_82xx { … }; /* ISP 83xx I/O Register Set structure */ struct device_reg_83xx { … }; #define INT_ENABLE_FW_MB … #define INT_MASK_FW_MB … /* remote register set (access via PCI memory read/write) */ struct isp_reg { … }; /* 256 x100 */ /* Semaphore Defines for 4010 */ #define QL4010_DRVR_SEM_BITS … #define QL4010_GPIO_SEM_BITS … #define QL4010_SDRAM_SEM_BITS … #define QL4010_PHY_SEM_BITS … #define QL4010_NVRAM_SEM_BITS … #define QL4010_FLASH_SEM_BITS … #define QL4010_DRVR_SEM_MASK … #define QL4010_GPIO_SEM_MASK … #define QL4010_SDRAM_SEM_MASK … #define QL4010_PHY_SEM_MASK … #define QL4010_NVRAM_SEM_MASK … #define QL4010_FLASH_SEM_MASK … /* Semaphore Defines for 4022 */ #define QL4022_RESOURCE_MASK_BASE_CODE … #define QL4022_RESOURCE_BITS_BASE_CODE … #define QL4022_DRVR_SEM_MASK … #define QL4022_DDR_RAM_SEM_MASK … #define QL4022_PHY_GIO_SEM_MASK … #define QL4022_NVRAM_SEM_MASK … #define QL4022_FLASH_SEM_MASK … /* nvram address for 4032 */ #define NVRAM_PORT0_BOOT_MODE … #define NVRAM_PORT0_BOOT_PRI_TGT … #define NVRAM_PORT0_BOOT_SEC_TGT … #define NVRAM_PORT1_BOOT_MODE … #define NVRAM_PORT1_BOOT_PRI_TGT … #define NVRAM_PORT1_BOOT_SEC_TGT … /* Page # defines for 4022 */ #define PORT_CTRL_STAT_PAGE … #define HOST_MEM_CFG_PAGE … #define LOCAL_RAM_CFG_PAGE … #define PROT_STAT_PAGE … /* Register Mask - sets corresponding mask bits in the upper word */ static inline uint32_t set_rmask(uint32_t val) { … } static inline uint32_t clr_rmask(uint32_t val) { … } /* ctrl_status definitions */ #define CSR_SCSI_PAGE_SELECT … #define CSR_SCSI_INTR_ENABLE … #define CSR_SCSI_RESET_INTR … #define CSR_SCSI_COMPLETION_INTR … #define CSR_SCSI_PROCESSOR_INTR … #define CSR_INTR_RISC … #define CSR_BOOT_ENABLE … #define CSR_NET_PAGE_SELECT … #define CSR_FUNC_NUM … #define CSR_NET_RESET_INTR … #define CSR_FORCE_SOFT_RESET … #define CSR_FATAL_ERROR … #define CSR_SOFT_RESET … #define ISP_CONTROL_FN_MASK … #define ISP_CONTROL_FN0_SCSI … #define ISP_CONTROL_FN1_SCSI … #define INTR_PENDING … /* ISP InterruptMask definitions */ #define IMR_SCSI_INTR_ENABLE … /* ISP 4022 nvram definitions */ #define NVR_WRITE_ENABLE … #define QL4010_NVRAM_SIZE … #define QL40X2_NVRAM_SIZE … /* ISP port_status definitions */ /* ISP Semaphore definitions */ /* ISP General Purpose Output definitions */ #define GPOR_TOPCAT_RESET … /* shadow registers (DMA'd from HA to system memory. read only) */ struct shadow_regs { … }; /* 8 x8 */ /* External hardware configuration register */ external_hw_config_reg; /* 82XX Support start */ /* 82xx Default FLT Addresses */ #define FA_FLASH_LAYOUT_ADDR_82 … #define FA_FLASH_DESCR_ADDR_82 … #define FA_BOOT_LOAD_ADDR_82 … #define FA_BOOT_CODE_ADDR_82 … #define FA_RISC_CODE_ADDR_82 … #define FA_GOLD_RISC_CODE_ADDR_82 … #define FA_FLASH_ISCSI_CHAP … #define FA_FLASH_CHAP_SIZE … #define FA_FLASH_ISCSI_DDB … #define FA_FLASH_DDB_SIZE … /* Flash Description Table */ struct qla_fdt_layout { … }; /* Flash Layout Table */ struct qla_flt_location { … }; struct qla_flt_header { … }; /* 82xx FLT Regions */ #define FLT_REG_FDT … #define FLT_REG_FLT … #define FLT_REG_BOOTLOAD_82 … #define FLT_REG_FW_82 … #define FLT_REG_FW_82_1 … #define FLT_REG_GOLD_FW_82 … #define FLT_REG_BOOT_CODE_82 … #define FLT_REG_ISCSI_PARAM … #define FLT_REG_ISCSI_CHAP … #define FLT_REG_ISCSI_DDB … struct qla_flt_region { … }; /************************************************************************* * * Mailbox Commands Structures and Definitions * *************************************************************************/ /* Mailbox command definitions */ #define MBOX_CMD_ABOUT_FW … #define MBOX_CMD_PING … #define PING_IPV6_PROTOCOL_ENABLE … #define PING_IPV6_LINKLOCAL_ADDR … #define PING_IPV6_ADDR0 … #define PING_IPV6_ADDR1 … #define MBOX_CMD_ENABLE_INTRS … #define INTR_DISABLE … #define INTR_ENABLE … #define MBOX_CMD_STOP_FW … #define MBOX_CMD_ABORT_TASK … #define MBOX_CMD_LUN_RESET … #define MBOX_CMD_TARGET_WARM_RESET … #define MBOX_CMD_GET_MANAGEMENT_DATA … #define MBOX_CMD_GET_FW_STATUS … #define MBOX_CMD_SET_ISNS_SERVICE … #define ISNS_DISABLE … #define ISNS_ENABLE … #define MBOX_CMD_COPY_FLASH … #define MBOX_CMD_WRITE_FLASH … #define MBOX_CMD_READ_FLASH … #define MBOX_CMD_CLEAR_DATABASE_ENTRY … #define MBOX_CMD_CONN_OPEN … #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT … #define DDB_NOT_LOGGED_IN … #define LOGOUT_OPTION_CLOSE_SESSION … #define LOGOUT_OPTION_RELOGIN … #define LOGOUT_OPTION_FREE_DDB … #define MBOX_CMD_SET_PARAM … #define SET_DRVR_VERSION … #define MAX_DRVR_VER_LEN … #define MBOX_CMD_EXECUTE_IOCB_A64 … #define MBOX_CMD_INITIALIZE_FIRMWARE … #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK … #define MBOX_CMD_REQUEST_DATABASE_ENTRY … #define MBOX_CMD_SET_DATABASE_ENTRY … #define MBOX_CMD_GET_DATABASE_ENTRY … #define DDB_DS_UNASSIGNED … #define DDB_DS_NO_CONNECTION_ACTIVE … #define DDB_DS_DISCOVERY … #define DDB_DS_SESSION_ACTIVE … #define DDB_DS_SESSION_FAILED … #define DDB_DS_LOGIN_IN_PROCESS … #define MBOX_CMD_GET_FW_STATE … #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS … #define MBOX_CMD_DIAG_TEST … #define MBOX_CMD_GET_SYS_INFO … #define MBOX_CMD_GET_NVRAM … #define MBOX_CMD_SET_NVRAM … #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS … #define MBOX_CMD_SET_ACB … #define MBOX_CMD_GET_ACB … #define MBOX_CMD_DISABLE_ACB … #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE … #define MBOX_CMD_GET_IPV6_DEST_CACHE … #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST … #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST … #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE … #define MBOX_CMD_GET_IP_ADDR_STATE … #define MBOX_CMD_SEND_IPV6_ROUTER_SOL … #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR … #define MBOX_CMD_SET_PORT_CONFIG … #define MBOX_CMD_GET_PORT_CONFIG … #define MBOX_CMD_SET_LED_CONFIG … #define MBOX_CMD_GET_LED_CONFIG … #define MBOX_CMD_MINIDUMP … /* Port Config */ #define ENABLE_INTERNAL_LOOPBACK … #define ENABLE_EXTERNAL_LOOPBACK … #define ENABLE_DCBX … /* Minidump subcommand */ #define MINIDUMP_GET_SIZE_SUBCOMMAND … #define MINIDUMP_GET_TMPLT_SUBCOMMAND … /* Mailbox 1 */ #define FW_STATE_READY … #define FW_STATE_CONFIG_WAIT … #define FW_STATE_WAIT_AUTOCONNECT … #define FW_STATE_ERROR … #define FW_STATE_CONFIGURING_IP … /* Mailbox 3 */ #define FW_ADDSTATE_OPTICAL_MEDIA … #define FW_ADDSTATE_DHCPv4_ENABLED … #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED … #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED … #define FW_ADDSTATE_LINK_UP … #define FW_ADDSTATE_ISNS_SVC_ENABLED … #define FW_ADDSTATE_LINK_SPEED_10MBPS … #define FW_ADDSTATE_LINK_SPEED_100MBPS … #define FW_ADDSTATE_LINK_SPEED_1GBPS … #define FW_ADDSTATE_LINK_SPEED_10GBPS … #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS … #define IPV6_DEFAULT_DDB_ENTRY … #define MBOX_CMD_CONN_OPEN_SESS_LOGIN … #define MBOX_CMD_GET_CRASH_RECORD … #define MBOX_CMD_GET_CONN_EVENT_LOG … #define MBOX_CMD_IDC_ACK … #define MBOX_CMD_IDC_TIME_EXTEND … #define MBOX_CMD_PORT_RESET … #define MBOX_CMD_SET_PORT_CONFIG … /* Mailbox status definitions */ #define MBOX_COMPLETION_STATUS … #define MBOX_STS_BUSY … #define MBOX_STS_INTERMEDIATE_COMPLETION … #define MBOX_STS_COMMAND_COMPLETE … #define MBOX_STS_COMMAND_ERROR … #define MBOX_ASYNC_EVENT_STATUS … #define MBOX_ASTS_SYSTEM_ERROR … #define MBOX_ASTS_REQUEST_TRANSFER_ERROR … #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR … #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM … #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED … #define MBOX_ASTS_LINK_UP … #define MBOX_ASTS_LINK_DOWN … #define MBOX_ASTS_DATABASE_CHANGED … #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED … #define MBOX_ASTS_SELF_TEST_FAILED … #define MBOX_ASTS_LOGIN_FAILED … #define MBOX_ASTS_DNS … #define MBOX_ASTS_HEARTBEAT … #define MBOX_ASTS_NVRAM_INVALID … #define MBOX_ASTS_MAC_ADDRESS_CHANGED … #define MBOX_ASTS_IP_ADDRESS_CHANGED … #define MBOX_ASTS_DHCP_LEASE_EXPIRED … #define MBOX_ASTS_DHCP_LEASE_ACQUIRED … #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED … #define MBOX_ASTS_DUPLICATE_IP … #define MBOX_ASTS_ARP_COMPLETE … #define MBOX_ASTS_SUBNET_STATE_CHANGE … #define MBOX_ASTS_RESPONSE_QUEUE_FULL … #define MBOX_ASTS_IP_ADDR_STATE_CHANGED … #define MBOX_ASTS_IPV6_DEFAULT_ROUTER_CHANGED … #define MBOX_ASTS_IPV6_LINK_MTU_CHANGE … #define MBOX_ASTS_IPV6_AUTO_PREFIX_IGNORED … #define MBOX_ASTS_IPV6_ND_LOCAL_PREFIX_IGNORED … #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD … #define MBOX_ASTS_INITIALIZATION_FAILED … #define MBOX_ASTS_SYSTEM_WARNING_EVENT … #define MBOX_ASTS_IDC_COMPLETE … #define MBOX_ASTS_IDC_REQUEST_NOTIFICATION … #define MBOX_ASTS_IDC_TIME_EXTEND_NOTIFICATION … #define MBOX_ASTS_DCBX_CONF_CHANGE … #define MBOX_ASTS_TXSCVR_INSERTED … #define MBOX_ASTS_TXSCVR_REMOVED … #define ISNS_EVENT_DATA_RECEIVED … #define ISNS_EVENT_CONNECTION_OPENED … #define ISNS_EVENT_CONNECTION_FAILED … #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR … #define MBOX_ASTS_SUBNET_STATE_CHANGE … /* ACB Configuration Defines */ #define ACB_CONFIG_DISABLE … #define ACB_CONFIG_SET … /* ACB/IP Address State Defines */ #define IP_ADDRSTATE_UNCONFIGURED … #define IP_ADDRSTATE_INVALID … #define IP_ADDRSTATE_ACQUIRING … #define IP_ADDRSTATE_TENTATIVE … #define IP_ADDRSTATE_DEPRICATED … #define IP_ADDRSTATE_PREFERRED … #define IP_ADDRSTATE_DISABLING … /* FLASH offsets */ #define FLASH_SEGMENT_IFCB … #define FLASH_OPT_RMW_HOLD … #define FLASH_OPT_RMW_INIT … #define FLASH_OPT_COMMIT … #define FLASH_OPT_RMW_COMMIT … /* generic defines to enable/disable params */ #define QL4_PARAM_DISABLE … #define QL4_PARAM_ENABLE … /*************************************************************************/ /* Host Adapter Initialization Control Block (from host) */ struct addr_ctrl_blk { … }; #define IP_ADDR_COUNT … #define IP_STATE_MASK … #define IP_STATE_SHIFT … struct init_fw_ctrl_blk { … }; #define PRIMARI_ACB … #define SECONDARY_ACB … struct addr_ctrl_blk_def { … }; /*************************************************************************/ #define MAX_CHAP_ENTRIES_40XX … #define MAX_CHAP_ENTRIES_82XX … #define MAX_RESRV_CHAP_IDX … #define FLASH_CHAP_OFFSET … struct ql4_chap_table { … }; struct dev_db_entry { … }; /*************************************************************************/ /* Flash definitions */ #define FLASH_OFFSET_SYS_INFO … #define FLASH_DEFAULTBLOCKSIZE … #define FLASH_EOF_OFFSET … #define FLASH_RAW_ACCESS_ADDR … #define BOOT_PARAM_OFFSET_PORT0 … #define BOOT_PARAM_OFFSET_PORT1 … #define FLASH_OFFSET_DB_INFO … #define FLASH_OFFSET_DB_END … struct sys_info_phys_addr { … }; struct flash_sys_info { … }; /* 200 */ struct mbx_sys_info { … }; struct about_fw_info { … }; struct crash_record { … }; struct conn_event_log_entry { … }; /************************************************************************* * * IOCB Commands Structures and Definitions * *************************************************************************/ #define IOCB_MAX_CDB_LEN … #define IOCB_MAX_SENSEDATA_LEN … #define IOCB_MAX_EXT_SENSEDATA_LEN … /* IOCB header structure */ struct qla4_header { … }; /* Generic queue entry structure*/ struct queue_entry { … }; /* 64 bit addressing segment counts*/ #define COMMAND_SEG_A64 … #define CONTINUE_SEG_A64 … /* 64 bit addressing segment definition*/ struct data_seg_a64 { … }; /* Command Type 3 entry structure*/ struct command_t3_entry { … }; /* Continuation Type 1 entry structure*/ struct continuation_t1_entry { … }; /* Parameterize for 64 or 32 bits */ #define COMMAND_SEG … #define CONTINUE_SEG … #define ET_COMMAND … #define ET_CONTINUE … /* Marker entry structure*/ struct qla4_marker_entry { … }; /* Status entry structure*/ struct status_entry { … }; /* Status Continuation entry */ struct status_cont_entry { … }; struct passthru0 { … }; struct passthru_status { … }; struct mbox_cmd_iocb { … }; struct mbox_status_iocb { … }; /* * ISP queue - response queue entry definition. */ struct response { … }; struct ql_iscsi_stats { … }; #define QLA8XXX_DBG_STATE_ARRAY_LEN … #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN … #define QLA8XXX_DBG_RSVD_ARRAY_LEN … #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN … #define QLA83XX_SS_OCM_WNDREG_INDEX … #define QLA83XX_SS_PCI_INDEX … #define QLA8022_TEMPLATE_CAP_OFFSET … #define QLA83XX_TEMPLATE_CAP_OFFSET … #define QLA80XX_TEMPLATE_RESERVED_BITS … struct qla4_8xxx_minidump_template_hdr { … }; #endif /* _QLA4X_FW_H */
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