/* * This file is part of the Chelsio FCoE driver for Linux. * * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include "csio_hw.h" #include "csio_init.h" static int csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win) { … } /* * Interrupt handler for the PCIE module. */ static void csio_t5_pcie_intr_handler(struct csio_hw *hw) { … } /* * csio_t5_flash_cfg_addr - return the address of the flash configuration file * @hw: the HW module * * Return the address within the flash where the Firmware Configuration * File is stored. */ static unsigned int csio_t5_flash_cfg_addr(struct csio_hw *hw) { … } /* * csio_t5_mc_read - read from MC through backdoor accesses * @hw: the hw module * @idx: index to the register * @addr: address of first byte requested * @data: 64 bytes of data containing the requested address * @ecc: where to store the corresponding 64-bit ECC word * * Read 64 bytes of data from MC starting at a 64-byte-aligned address * that covers the requested address @addr. If @parity is not %NULL it * is assigned the 64-bit ECC word for the read data. */ static int csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, uint64_t *ecc) { … } /* * csio_t5_edc_read - read from EDC through backdoor accesses * @hw: the hw module * @idx: which EDC to access * @addr: address of first byte requested * @data: 64 bytes of data containing the requested address * @ecc: where to store the corresponding 64-bit ECC word * * Read 64 bytes of data from EDC starting at a 64-byte-aligned address * that covers the requested address @addr. If @parity is not %NULL it * is assigned the 64-bit ECC word for the read data. */ static int csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, uint64_t *ecc) { … } /* * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window * @hw: the csio_hw * @win: PCI-E memory Window to use * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1 * @addr: address within indicated memory type * @len: amount of memory to transfer * @buf: host memory buffer * @dir: direction of transfer 1 => read, 0 => write * * Reads/writes an [almost] arbitrary memory region in the firmware: the * firmware memory address, length and host buffer must be aligned on * 32-bit boundaries. The memory is transferred as a raw byte sequence * from/to the firmware's memory. If this memory contains data * structures which contain multi-byte integers, it's the callers * responsibility to perform appropriate byte order conversions. */ static int csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr, u32 len, uint32_t *buf, int dir) { … } /* * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values * @hw: the csio_hw * * This function creates files in the debugfs with external memory region * MC0 & MC1. */ static void csio_t5_dfs_create_ext_mem(struct csio_hw *hw) { … } /* T5 adapter specific function */ struct csio_hw_chip_ops t5_ops = …;
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